packed vs unpacked vectors in system verilog

Question

Looking at some code I\'m maintaining in System Verilog I see some signals that are defined like this:

node [range_hi:range_lo]x;

and other

Answer 1

Before knowing what exactly packed and unpacked arrays are, lets also see how you can know which array is what, just by their declaration. Packed arrays have an object name comes before size declaration. For example:

bit [3][7] a;

Unpacked array have an object name comes after size declaration. For example:

bit a[3];

Packed array make memory whereas Unpacked dont. You can access/declare unpacked array like this also

reg unpacked_array [7:0] = '{0,0,0,0,0,0,0,1};

You can mix both packed and unpacked array to make a multidimensional memory. For example:

bit [3:0][7:0]a[2:0].

It makes an array of 4 (i.e. 4*8) bytes with depth of 3.