rdtsc accuracy across CPU cores

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一生所求
一生所求 2020-11-28 22:53

I am sending network packets from one thread and receiving replies on a 2nd thread that runs on a different CPU core. My process measures the time between send & receiv

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  •  情歌与酒
    2020-11-28 23:43

    X86_FEATURE_CONSTANT_TSC + X86_FEATURE_NONSTOP_TSC bits in cpuid (edx=x80000007, bit #8; check unsynchronized_tsc function of linux kernel for more checks)

    Intel's Designer's vol3b, section 16.11.1 Invariant TSC it says the following

    "16.11.1 Invariant TSC

    The time stamp counter in newer processors may support an enhancement, referred to as invariant TSC. Processor's support for invariant TSC is indicated by CPUID.80000007H:EDX[8].

    The invariant TSC will run at a constant rate in all ACPI P-, C-. and T-states. This is the architectural behavior moving forward. On processors with invariant TSC support, the OS may use the TSC for wall clock timer services (instead of ACPI or HPET timers). TSC reads are much more efficient and do not incur the overhead associated with a ring transition or access to a platform resource."

    So, if TSC can be used for wallclock, they are guaranteed to be in sync.

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