How does signal assignment work in a process?

Question

I learned that a signal is not changed immediately when encountering an expression, but when the process ends. In this example here:

...
signal x,y,z : bit;
         


        

Answer 1

Variables get updated as you assign them. Signals get update in the next delta cycle (at the earliest).

a := '1'; -- variable
assert a = 1;
b <= '1'; -- signal
computationUsing(b); --reads old value of b
-- new value will be visible after this process ends or some time passes

Jan Decaluwe explains this stuff in more detail here: http://www.sigasi.com/content/vhdls-crown-jewel