we have some C++ code that we need to create a make file in. Each .h and .C pair create an object and then some objects are linked together to form a executable. Pretty standard
This is an example of a pattern rule, it should work fine in gmake
. For very simple builds like this you can mostly rely on the implicit rules. The main thing you have to specify in the target you want to build and its dependencies:
CXXFLAGS:=-g -O -Iincludes
LDFLAGS:=-lm
SRCS:=$(shell ls *.C) # select all .C files as source
OBJS:=$(substr .C,.o,$(SRCS) # list the corresponding object files
foo : $(OBJS)
Note the use of simply expanded variable assignment operator (:=
) rather than the recursive assignment operator (=
) which can reduce the amount of reprocessing make does in more complicated builds.