Microarchitectural zeroing of a register via the register renamer: performance versus a mov?

Question

I read on a blog post that recent X86 microarchitectures are also able to handle common register zeroing idioms (such as xor-ing a register with itself) in the register renamer;

Answer 1

In addition to no latency, another benefit to zero idioms is that on modern Intel microarchitectures, the renaming, move elimination and zero idiom stage happens before even the scheduling of uops. Consequently, while a zero move idiom exists as a uop, it doesn't compete for execution ports allowing more ILP.

Since zero idioms are detected and removed by the renamer, they have no execution latency.