Is initialization necessary?

Question

In VHDL, is initialization necessary when creating a signal or a vector? What happens if one forgets to initialize a signal or integer value?

Answer 1

In simulation, everything in VHDL is initialised at the start to the "left-most" element of the range which represents them.

So, std_logic will get 'U', boolean will get false, integer will get a big negative number. Any enumerated types you've defined yourself will init to their first member. etc.

You can override this with an explicit initialisation:

variable i : integer := 0;

the simulator will then use your initialisation.

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When it comes to synthesising your code, in an ASIC, explicit initialisations are ignored (there's no silicon to support them!), and everything initialises unpredictably. So you have a reset pin and explicit code which assigns the value you want when that pin is asserted.

When you target an FPGA and don't explicitly initialise, most of the time things will initialise to something 'like zero', but you can't rely on it (sometimes inverters are pushed around and things look like they've inited to 'one'). So you have a reset pin and explicit code which assigns the value you want when that pin is asserted.

Some synthesisers (XST at least) will support explicit initialisations and pass them into the netlist so that you can rely on them. In this case you can still have a reset signal - which can do something different so a particular flipflop could initialise to one value and reset to another!