amd-processor

问题 I was trying to figure out a way to perform offline compilation of OpenCL kernels without installing Graphics cards. I have installed the SDK's. Does anyone has any experience with compiling OpenCL Kernels without having the graphics cards installed for both any one of them NVIDIA or AMD. I had asked a similar question on AMD forums (http://devgurus.amd.com/message/1284379). NVIDIA forums for long are in accessible so couldn't get any help from there. Thanks 回答1: AMD has an OpenCL extension

问题 I'm trying to understand the meaning of the perf events: dTLB-loads and dTLB-stores? 回答1: When virtual memory is enabled, the virtual address of every single memory access needs to be looked up in the TLB to obtain the corresponding physical address and determine access permissions and privileges (or raise an exception in case of an invalid mapping). The dTLB-loads and dTLB-stores events represent a TLB lookup for a data memory load or store access, respectively. The is the perf definition of

问题 I'm trying to understand the meaning of the perf events: dTLB-loads and dTLB-stores? 回答1: When virtual memory is enabled, the virtual address of every single memory access needs to be looked up in the TLB to obtain the corresponding physical address and determine access permissions and privileges (or raise an exception in case of an invalid mapping). The dTLB-loads and dTLB-stores events represent a TLB lookup for a data memory load or store access, respectively. The is the perf definition of

问题 I know that Numpy can use different backends like OpenBLAS or MKL. I have also read that MKL is heavily optimized for Intel, so usually people suggest to use OpenBLAS on AMD, right? I use the following test code: import numpy as np def testfunc(x): np.random.seed(x) X = np.random.randn(2000, 4000) np.linalg.eigh(X @ X.T) %timeit testfunc(0) I have tested this code using different CPUs: On Intel Xeon E5-1650 v3 , this code performs in 0.7s using 6 out of 12 cores . On AMD Ryzen 5 2600 , this

问题 I have MASM synchronizing code for an application which runs on both Intel and AMD x86 machines. I'd like to enhance it using the Intel TSX prefixes, specifically XACQUIRE and XRELEASE. If I modify my code correctly for Intel, what will happen when I attempt to run it on AMD machines? Intel says that these were designed to be backwards compatible, presumably meaning they do nothing on Intel CPUs without TSX. I know that AMD has not implemented TSX. But are these prefixes safe to run on AMD

问题 I have MASM synchronizing code for an application which runs on both Intel and AMD x86 machines. I'd like to enhance it using the Intel TSX prefixes, specifically XACQUIRE and XRELEASE. If I modify my code correctly for Intel, what will happen when I attempt to run it on AMD machines? Intel says that these were designed to be backwards compatible, presumably meaning they do nothing on Intel CPUs without TSX. I know that AMD has not implemented TSX. But are these prefixes safe to run on AMD

问题 I have MASM synchronizing code for an application which runs on both Intel and AMD x86 machines. I'd like to enhance it using the Intel TSX prefixes, specifically XACQUIRE and XRELEASE. If I modify my code correctly for Intel, what will happen when I attempt to run it on AMD machines? Intel says that these were designed to be backwards compatible, presumably meaning they do nothing on Intel CPUs without TSX. I know that AMD has not implemented TSX. But are these prefixes safe to run on AMD

问题 I try to build Android app from Android Studio. I tried to install HAXM from Android Studio installer but I've an error: Intel Virtualization Technology is already enabled in my BIOS. And the Hyper-V is already disabled on Windows 10. 回答1: For Ryzen on Windows 10, use the latest stable instead of canary. Enable virtualization in BIOS. Remove HAXM. Turn off Hyper-V , Windows Hypervisor platform , Windows Sandbox (depends on your windows version, old versions may not have all). REBOOT Launch

问题 The issue of the repz ret has been covered here [1] as well as in other sources [2, 3] quite satisfactorily. However, reading neither of these sources, I found answers to the following: What is the actual penalty in a quantitative comparison with ret or nop; ret ? Especially in the latter case – is decoding one extra instruction (and an empty one at that!) really relevant, when most functions either have 100+ of those or get inlined? Why did this never get fixed in AMD K8, and even made its

问题 Modern Intel and AMD chips have large store buffers to buffer stores before commit to the L1 cache. Conceptually, these entries hold the store data and store address. For the address part, do these buffer entries hold virtual or physical addresses, or both? 来源： https://stackoverflow.com/questions/61190976/does-the-store-buffer-hold-physical-or-virtual-addresses-on-modern-x86