I'm using Ubuntu Linux 14.04 LTS with Altera Quartus 15.0 web-edition and I'm having a hard time simulate my design due to licensing errors. I'm designing an LCD_driver for the VEEK-MT's LCD touch screen by terasic with the Cyclone IV EP4CE115 by Altera.
Honestly, I don't have much of experience with simulation software like ModelSim-Altera but I do know how to use .vwf files and simulate with them, I know as well how to use signaltap logic analyzer. After creating the usinversity program .vwf files, I compile the project, I press run functional simulation and I get a window with the following content:
Determining the location of the ModelSim executable...
Using: /home/bdoronnb/Downloads/Quartus/15.0/ModelSim/modelsim_ase/bin
To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used.
**** Generating the ModelSim Testbench ****
quartus_eda --gen_testbench --check_outputs=on --tool=modelsim_oem --format=verilog --write_settings_files=off test5 -c test5 --vector_source="/path/to/Altera/projects/test/5/test5.vwf" --testbench_file="/path/to/Altera/projects/test/5/simulation/qsim/test5.vwf.vt"
Inconsistency detected by ld.so: dl-close.c: 762: _dl_close: Assertion `map->l_init_called' failed! Info: *******************************************************************Info: Running Quartus II 64-Bit EDA Netlist Writer Info: Version 15.0.0 Build 145 04/22/2015 SJ Web Edition Info: Copyright (C) 1991-2015 Altera Corporation. All rights reserved. Info: Your use of Altera Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Altera Program License Info: Subscription Agreement, the Altera Quartus II License Agreement,
Info: the Altera MegaCore Function License Agreement, or other
Info: applicable license agreement, including, without limitation,
Info: that your use is for the sole purpose of programming logic
Info: devices manufactured by Altera and sold by Altera or its
Info: authorized distributors. Please refer to the applicable
Info: agreement for further details. Info: Processing started: Sun Aug 9 22:18:46 2015Info: Command: quartus_eda --gen_testbench --check_outputs=on --tool=modelsim_oem --format=verilog --write_settings_files=off test5 -c test5 --vector_source=/path/to/Altera/projects/test/5/test5.vwf --testbench_file=/path/to/Altera/projects/test/5/simulation/qsim/test5.vwf.vtWarning (201007): Can't find port "h_counter" in designWarning (201007): Can't find port "h_counter[10]" in designWarning (201007): Can't find port "h_counter[9]" in designWarning (201007): Can't find port "h_counter[8]" in designWarning (201007): Can't find port "h_counter[7]" in designWarning (201007): Can't find port "h_counter[6]" in designWarning (201007): Can't find port "h_counter[5]" in designWarning (201007): Can't find port "h_counter[4]" in designWarning (201007): Can't find port "h_counter[3]" in designWarning (201007): Can't find port "h_counter[2]" in designWarning (201007): Can't find port "h_counter[1]" in designWarning (201007): Can't find port "h_counter[0]" in designWarning (201007): Can't find port "v_counter" in designWarning (201007): Can't find port "v_counter[9]" in designWarning (201007): Can't find port "v_counter[8]" in designWarning (201007): Can't find port "v_counter[7]" in designWarning (201007): Can't find port "v_counter[6]" in designWarning (201007): Can't find port "v_counter[5]" in designWarning (201007): Can't find port "v_counter[4]" in designWarning (201007): Can't find port "v_counter[3]" in designWarning (201007): Can't find port "v_counter[2]" in designWarning (201007): Can't find port "v_counter[1]" in designWarning (201007): Can't find port "v_counter[0]" in designWarning (201007): Can't find port "HSD_s" in designWarning (201007): Can't find port "VSD_s" in designInfo (201000): Generated Verilog Test Bench File /path/to/Altera/projects/test/5/simulation/qsim/test5.vwf.vt for simulationInfo: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 25 warnings Info: Peak virtual memory: 1088 megabytes Info: Processing ended: Sun Aug 9 22:18:47 2015 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 Completed successfully.Completed successfully.
**** Generating the functional simulation netlist ****
quartus_eda --write_settings_files=off --functional=on --flatten_buses=off --simulation --tool=modelsim_oem --format=verilog --output_directory="/path/to/Altera/projects/test/5/simulation/qsim/" test5 -c test5
Inconsistency detected by ld.so: dl-close.c: 762: _dl_close: Assertion `map->l_init_called' failed! Info: *******************************************************************Info: Running Quartus II 64-Bit EDA Netlist Writer Info: Version 15.0.0 Build 145 04/22/2015 SJ Web Edition Info: Copyright (C) 1991-2015 Altera Corporation. All rights reserved. Info: Your use of Altera Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Altera Program License Info: Subscription Agreement, the Altera Quartus II License Agreement,
Info: the Altera MegaCore Function License Agreement, or other
Info: applicable license agreement, including, without limitation,
Info: that your use is for the sole purpose of programming logic
Info: devices manufactured by Altera and sold by Altera or its
Info: authorized distributors. Please refer to the applicable
Info: agreement for further details. Info: Processing started: Sun Aug 9 22:18:53 2015Info: Command: quartus_eda --write_settings_files=off --functional=on --flatten_buses=off --simulation=on --tool=modelsim_oem --format=verilog --output_directory=/path/to/Altera/projects/test/5/simulation/qsim/ test5 -c test5Info (204019): Generated file test5.vo in folder "/path/to/Altera/projects/test/5/simulation/qsim//" for EDA simulation toolInfo: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings Info: Peak virtual memory: 1093 megabytes Info: Processing ended: Sun Aug 9 22:18:55 2015 Info: Elapsed time: 00:00:02 Info: Total CPU time (on all processors): 00:00:01 Completed successfully.**** Generating the ModelSim .do script ****
/path/to/Altera/projects/test/5/simulation/qsim/test5.do generated.
Completed successfully.
**** Running the ModelSim simulation ****
/home/bdoronnb/Downloads/Quartus/15.0/ModelSim/modelsim_ase/bin/vsim -c -do test5.do
/home/bdoronnb/Downloads/Quartus/15.0/ModelSim/modelsim_ase/bin/../linux/vish: error while loading shared libraries: libXft.so.2: cannot open shared object file: No such file or directory Error.
Any help is appreciated.