Target-specific Variables as Prerequisites in a Makefile

Question

I'm trying to write a GNU make Makefile which has a load of similar targets, where the build commands vary slightly between them. I'm trying to use target-specific variables to represent these variations. Some of these variable values refer to files I want to use as prerequisites. For example:

target_1:special_filename=target1_prereq
target_2:special_filename=target2_prereq

target_1 target_2: common_filename $(special_filename)
    do_something common_filename --a-weird-option=$(special_filename)

When I call 'make target_1', I want it to make target1_prereq if it doesn't exist. At the moment, it doesn't seem to use target1_prereq as a prerequisite, even though the build command (do_something) is called with the right parameter.

I'm using GNU Make 3.80.

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Edit: A few more complications from the real system. Some of the variables are themselves based on the values of other variables. Manually specifying the prerequisites wouldn't scale. A slightly more complicated example:

target_1:special_filename_base=target1_prereq
target_2:special_filename_base=target2_prereq

some_filename_a = $(special_filename_base).exta
some_filename_b = $(special_filename_base).extb

target_1 target_2: common_filename $(special_filename_b) $(special_filename_a)
    do_something common_filename --a-weird-option=$(special_filename_a) --second=$(special_filename_b)

Answer 1

A target-specific variable is defined only in the target's commands (or in other target-specific assignments); it can't be used as one of the target's prereqs. I don't think there's a clean way to do what you want in Make, but there are several kludgey approaches, such as the following:

EXTENSIONS = .exta .extb
target_1: $(addprefix target1_prereq,$(EXTENSIONS))
target_2: $(addprefix target2_prereq,$(EXTENSIONS))

target_1 target_2: common_filename
    do_something common_filename --a-weird-option=$(filter %.exta,$^) --second=$(filter %.extb,$^)

Answer 2

As a simple workaround:

target_1:special_filename=target1_prereq
target_1:target1_prereq
target_2:special_filename=target2_prereq
target_2:target2_prereq

target_1 target_2: common_filename $(special_filename)
    do_something common_filename --a-weird-option=$(special_filename)

There is some redundancy, but it is localized, so it's not too bad.

Answer 3

I've found a rather clean way of side-stepping this limitation. It'd go something like this:

target_1:export special_filename_base=target1_prereq
target_2:export special_filename_base=target2_prereq

some_filename_a = $(special_filename_base).exta
some_filename_b = $(special_filename_base).extb

target_1 target_2:
    $(MAKE) -f $(firstword $(MAKEFILE_LIST)) target-proxy

target-proxy: common_filename $(special_filename_b) $(special_filename_a)
    do_something common_filename --a-weird-option=$(special_filename_a) --second=$(special_filename_b)

Two important points:

1. export the target variables, so that they'll be accessible when we re-run the Makefile.
2. Create a proxy target that has all the original prerequisites of target_1 target_2 and in target_1 target_2 invoke the Makefile again with this proxy target. Since the target specific variables will have values by then (we are in the recipe by that time) and they were exported, they'll be available in target-proxy - voila :)

The downside of this approach is that we are creating another make process - if it's just another one then it's probably ok, but YMMV so be extra careful.