进入Non_project模式：
vivado -mode tcl
source top.tcl
top.tcl的内容为：
set _part “型号”
file mkdir project
read_verilog [glob *.v]
read_ip ip.xci //IP ooc
set_property file_type {Verilog Header} [get_files include.v] //beforce this step ,ensure that include.v has already read in
read_xdc xxx.xdc
synth_design -top "top module" -part "型号"
write_checkpoint -force "综合后dcp文件名"
#******************ILA***********************************#
create_debug_core u_ila_0 ila
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU false [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_cores u_ila_0/clk]
connect_debug_port u_ila0/clk [get_nets [list xxx]]]
set_property port_width 2 [get_debug_cores u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list xxx]]]
create_debug_port u_ila_0 probe
set_property port_width 2 [get_debug_cores u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list xxx]]]
#******************ILA***********************************#
opt_design
write_debug_probes -force xxx.ltx
#read_checkpoint -incremental routed.dcp //增量实现
place_design
route_design
write_checkpoint -force "布局布线后dcp文件名"
write_bitstream -force "Bit文件名"
来源：CSDN
作者：290640862
链接：https://blog.csdn.net/qq_34162142/article/details/103808160