VHDL Syntax error with if then process

问题

library ieee;
use ieee.std_logic_1164.all;

entity basic_shift_register_with_multiple_taps is

    generic
    (
        DATA_WIDTH : natural := 8

    );

    port 
    (
        clk          : in std_logic;
        enable       : in std_logic;
        sr_one       : in std_logic_vector((DATA_WIDTH-1) downto 0);
        sr_two       : in std_logic_vector((DATA_WIDTH-1) downto 0);
        sr_out       : out std_logic_vector(2*(DATA_WIDTH-1) downto 0)
    );

end entity ;

architecture rtl of basic_shift_register_with_multiple_taps is


    signal sig_out  :std_logic_vector(2*(DATA_WIDTH-1) downto 0);
    variable count  : integer := 0;
    variable count1 : integer := 0;

begin

    process (clk,enable,sr_one,sr_two,sig_out)

    begin

        if(enable = '0' or count = 16) then 
            count := 0;
            count1 := 0;
        else if (clk'event and clk='1') then
            sig_out(count) <= sr_one(count1);

            count := count + 1;

        else --if (clk'event and clk='0') then--
            sig_out(count) <= sr_two(count1);
            count := count + 1;

        end if;

        count1 := count1 + 1;   


(54)    end process;

    sr_out <= sig_out;

(58) end rtl;

errors:

Error (10500): VHDL syntax error at teste.vhd(54) near text "process"; expecting "if"

Error (10500): VHDL syntax error at teste.vhd(58) near text "rtl"; expecting "if"

回答1:

Your problem is that your second if statement

if (clk'event and clk='1') then

has no end if associated with it. So, when the compiler gets to line 54, it encounters an end process before the end if it was expecting. Instead of this

if(enable = '0' or count = 16) then 
    count := 0;
    count1 := 0;
else if (clk'event and clk='1') then
    sig_out(count) <= sr_one(count1);

    count := count + 1;

else --if (clk'event and clk='0') then--
    sig_out(count) <= sr_two(count1);
    count := count + 1;

end if;

do this:

if(enable = '0' or count = 16) then 
    count := 0;
    count1 := 0;
else
    if (clk'event and clk='1') then
        sig_out(count) <= sr_one(count1);
        count := count + 1;
    else --if (clk'event and clk='0') then--
        sig_out(count) <= sr_two(count1);
        count := count + 1;
    end if;
end if;

However, if you are intending to synthesis this, your syntax error is the least of your worries. See this answer.

来源：https://stackoverflow.com/questions/41567501/vhdl-syntax-error-with-if-then-process

标签

vhdl