How to force GNU make to recompile the same object file used in two targets with different FLAGS

问题

Suppose you have have a makefile containing two targets as in the following:

# targetA
X86CPPTARGET += targetA
targetA,SRCS = FILEA.cpp  FILEB.cpp commonFile.cpp
targetA.so,DEPSOL = libUsedByCommon1.cpp
targetA,CPPFLAGS += -Ifakeinclude -std=c++11

# tartargetBgetA
X86CPPTARGET += targetB
targetB,SRCS = FILEC.cpp  FILED.cpp commonFile.cpp
targetA.so,DEPSOL = libUsedByCommon2.cpp
targetB,CPPFLAGS += -std=c++11

targetA and targetB share a file, namely, commonFile.cpp which contains a number of #included headers. commonFile.o is created only once by GNU make and reused during the compilation of targetB.

The CPPFLAGS present in targetA makes the compiler use an include that contains more symbols that the one that is in the default include directory. libUsedByCommon2 does not export all the additional symbols that are contained in the header in the fakeinclude directory and at link time, this results in undefined reference.

The workaround I am usingat the moment is to create a symbolic link to commonFile.cpp and use that in my makefile in only one of the target.

# targetA
X86CPPTARGET += targetA
targetA,SRCS = FILEA.cpp  FILEB.cpp commonFile.cpp
targetA.so,DEPSOL = libUsedByCommon1.cpp
targetA,CPPFLAGS += -Ifakeinclude -std=c++11

# tartargetBgetA
X86CPPTARGET += targetB
targetB,SRCS = FILEC.cpp  FILED.cpp **commonFile_symbolic_link.cpp**
targetA.so,DEPSOL = libUsedByCommon2.cpp
targetB,CPPFLAGS += -std=c++11

Is there a cleaner solution to this problem? Is there a way to force GNU make to recompile commonFile.cpp when a different include path is being used?

回答1:

You could create two new targets who are dependent on the same C file with different build commands like the following example...

commonFileA.o: commonFile.cpp
    $(CC) -o $@ $^ -FlagsA

commonFileB.o: commonFile.cpp
    $(CC) -o $@ $^ -FlagsB

You can then use "commonFileA.o" as a dependency to link in the version with those particular flags etc...

回答2:

You should probably try to compile the same source file but with two different output object files:

a0.o: MYFLAGS := foo bar
a0.o: a.c
a1.o: MYFLAGS := baz cux
a1.o: a.c

And then, for the depending targets, use either a0.o or a1.o as prerequisite.

回答3:

One way I have done this is to set a variable and then recursively call make with a specific target. One advantage of this method is you can specify your targets only once.

This is an incomplete extract to show the technique:

all: debug release

debug:
    @echo -e "\n====== BUILDING DEBUG PROGRAM ======\n"
    @FLAGS="$(CXXFLAGS_DBG)" SUFFIX="-debug" $(MAKE) general

release:
    @echo -e "\n====== BUILDING RELEASE PROGRAM ======\n"
    @FLAGS="$(CXXFLAGS_REL)" $(MAKE) general

general: $(PROGRAM)$(SUFFIX)

$(PROGRAM)$(SUFFIX): $(SRC)/program.cpp
    $(CXX) $(FLAGS) -o $@ $^

来源：https://stackoverflow.com/questions/53709886/how-to-force-gnu-make-to-recompile-the-same-object-file-used-in-two-targets-with

标签

c++

makefile

clearcase