Data visibility on multi-core processor by single thread

问题

In a single thread program, how are changes made by thread in core 1 made visible to another core 2, so that after a context switch the thread (now running on core 2) will have updated value?

Consider the following example:

1. The value in main memory for variable x is 10.

2. The thread runs on core 1 and changes x to 5, which is still in cache and not yet flushed to main memory as we are not using any memory barrier.

3. A context switch occurs and the thread moves from core 1 to core 2.

4. The thread reads the value of x.

What would be the value of x if thread resumes execution in core 2 after the context switch?

If "cache coherence" manages consistency to handle a case like above then why do we need for explicit locking (or any read/write barrier) in a multi-threaded program?

回答1:

Considering your first question, context switches also preserve the register contents. Therefore, the threads sees the latest value, even if moved to another core (or CPU).

However for a multi-threaded program, CPU registers are distinct for different threads (regardless on how many cores the threads are executed), and registers are not part of cache coherency.

Therefore, I think, a multi-threaded program does need to make sure the values in the registers are up-to-date with the values in the main memory. (Cache coherence only makes sure that the CPU cache is up-to-date with the memory). Therefore, I suppose, you need a barrier to synchronize the register with the memory.

You can understand it as this: the program essentially operates only on the main memory. However, compilers optimise access to main memory and use registers for intermediate operations. Thus, the program access only memory and registers. However, the CPU also introduces its own cache of the memory. Reads and writes from/to the memory are internally (by the CPU) optimised by the cache. Cache coherency only ensures within the CPU, that the cache is up-to-date (and therefore, a program accessing memory gets the correct value.)

To sum up:

• Cache coherence ensures cache and memory are up-to-date, it is out of the control of the program, as it is internal to the CPU.
• Context switches are handled by the operating system, which ensures correct values of registers when it moves threads to different cores.
• Memory barriers ensure that the registers and memory are up-to-date, this is what the program has to ensure.

来源：https://stackoverflow.com/questions/40256057/data-visibility-on-multi-core-processor-by-single-thread