Difference of SystemVerilog data types (reg, logic, bit)

问题

There are different data types in systemverilog that can be used like the following:

reg [31:0] data;
logic [31:0] data;
bit [31:0] data;

How does the three of them differ?

回答1:

reg and wire were the original types. Wires are constantly assigned and regs are evaluated at particular points, the advantage here is for the simulator to make optimisations.

wire w_data;
assign w_data = y;

// Same function as above using reg
reg r_data;
always @* 
  r_data = y ;

A common mistake when learning Verilog is to assume the a reg type implies a register in hardware. The earlier optimisation for the simulator can be done through the context of its usage.

This introduces logic which can be used in place of wire and reg.

logic  w_data;
assign w_data = y;

// Same function as above using reg
logic r_data;
always @* 
  r_data = y ;

The type bit and byte have also been created that can only hold 2 states 0 or 1 no x or z. byte implies bit [7:0]. Using these types offers a small speed improvement but I would recommend not using them in RTL as your verification may miss uninitialized values or critical resets.

The usage of bit and byte would be more common in testbench components, but can lead to issues in case of having to drive x's to stimulate data corruption and recovery.

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Update

At the time of writing I was under the impression that logic could not be used for tristate, I am unable to find the original paper that I based this on. Until further updates, comments or edits, I revoke my assertion that logic can not be used to create tri-state lines.

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The tri type has been added, for explicitly defining a tri-state line. It is based on the properties of a wire, logic is based on the properties of a reg.

tri t_data;
assign t_data = (drive) ? y : 1'bz ;

If you no longer have to support backwards compatibility Verilog then I would recommend switching to using logic and tri. Using logic aids re-factoring and and tri reflects the design intent of a tristate line.

回答2:

• The choice of the name reg turned out to be a mistake, because the existence of registers is instead inferred based on how assignments are performed. Due to this, use of reg is essentially deprecated in favor of logic, which is actually the same type.

• logic is a 1-bit, 4-state data type

• bit is a 1-bit, 2-state data type which may simulate faster than logic
• If a logic is also declared as a wire, it has the additional capability of supporting multiple drivers. Note that by default wire is equivalent to wire logic.
• In general, the "nets" (such as wire and tri) are most suitable for designing communication buses.

Practically speaking, for RTL it usually doesn't matter whether you declare with reg, or logic, or wire. However, if you have to make an explicit declaration of a 4-state type (as opposed to when you don't), you should typically choose logic since that is what is intended by the language.

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Related articles:

• What’s the deal with those wire’s and reg’s in Verilog
• An analysis of the "logic" data type by Cliff Cummings - 20021209

回答3:

As I'm unable to add a comment I've to write what looks like a new answer but isn't. Sigh!

@e19293001, @Morgan, logic defines a 4-state variable unlike bit, and hence a logic variable can be used to store 1'bz so the following code is valid and compiles:

logic t_data;
assign t_data = (drive) ? y : 1'bz ;

But I agree that to reflect the design intent tri should be used instead of logic in these cases (although I must say I don't see people using tri instead of logic/wire too often).

回答4:

Logic data type doesn't permit multiple driver. The last assignment wins in case of multiple assignment .Reg/Wire data type give X if multiple driver try to drive them with different value. Logic data type simply assign the last assignment value.

回答5:

reg and logic are exactly the same. These data types appear inside the always or initial blocks and store values i.e. always @(a) b <= a;, the reg b gets evaluated only when 'a' changes but otherwise it simply stores the value it has been assigned last.

wire are just simply connections and need to continuously driven. I agree that they can behave identical as @Morgan mentioned, but they can be imagined as a piece of hard wire, the value of which changes only the value at the other end or the source changes.

来源：https://stackoverflow.com/questions/13282066/difference-of-systemverilog-data-types-reg-logic-bit