Instantiation of a module in verilog

问题

I am getting an error in instantiating a module in verilog file. I am instantiating like this:

module lab3(input clk,set,reset,plus,minus,start,button,output reg [3:0]led,output reg [6:0]y);

wire [3:0] indicesgu[3:0];
reg [1:0] going;
reg alsogoing,yes;


if (going==1 && alsogoing)
begin
 up_counter up_0 ( 
 indicesgu  ,
 indices    ,
 alsogoing
 );
end

endmodule

and my up_counter module starts as:

module up_counter(input [3:0] indices_in [3:0],output [3:0]indices[3:0],output alsogoing);

reg [3:0]indices[3:0];
reg [2:0]current,setting;

endmodule

when I try to compile in Xilinx, it says unexpected token up_counter. Thanks in advance.

回答1:

There are several problems with your lab3 module.

1. You need an endmodule at the end.
2. You should not instantiate up_counter inside an if. Verilog does not support conditional instances like that.
3. You need an opening paren after the instance name up_0.

回答2:

You have (multiple) syntax errors in your code. One of them is you need brackets () around your component port list

up_counter up_0 (indicesgu  ,
                 indices    ,
                 alsogoing
                 );

check the Verilog syntax for more info.

This will at least fix the 'unexpected token up_counter' error.

来源：https://stackoverflow.com/questions/14522422/instantiation-of-a-module-in-verilog