问题
I am trying to simulate my VHDL file, but am running into the following error:
# ** Error: (vcom-11) Could not find work.lab1.
#
# ** Error: (vcom-1195) Cannot find expanded name "work.lab1".
#
# ** Error: Unknown expanded name.
# ** Error: VHDL Compiler exiting
# ** Error: c:/altera/12.1/modelsim_ase/win32aloem/vcom failed.
# Error in macro ./DE2_TOP_run_msim_rtl_vhdl.do line 8
# c:/altera/12.1/modelsim_ase/win32aloem/vcom failed.
# while executing
# "vcom -93 -work work"
I compiled the code successfully through both Quartus II and the ModelSim compiler before attempting to simulate. I do have a lab1 entity and architecture in my code (I can even see it in the Design Units tab of the Quartus Project Navigator), so I don't really understand this error. Anyone know what's causing this?
回答1:
When the simulator is compiling the toplevel (DE2_TOP) it want to know how the used components are like. So, you should have compiled the lowerlevel components before compiling the upperlevel components.
What I do most of the times to fix this is compiling all components in correct order and then use the 'vmake' ('vmake -work work > work.vmake') command of Modelsim to generate a makefile out of the library (work). Once you have the makefile you can execute it with (make -f work.vmake). And all files will be compiled in order.
Note: Verilog is much more relaxed in those things...
来源：https://stackoverflow.com/questions/14539642/vhdl-modelsim-could-not-find-entity