GNU Makefile “preprocessor”?

问题

Is there an option to output the "preprocessed" makefile, something equivalent to the GCC's -E option?

I have a project comprised of an hierarchy of dozens of modules, each with its makefile. The build is invoked from a master makefile. That master makefile contains includes, variable definitions, command line option dependent variables, etc.

So, essentially, I am looking for the processed makefile, including all substitutions.

回答1:

Not that I'm aware of. The closest thing you can get to this is the output from make -qp (or similar) which will dump the make database out at you.

Part of the problem with this request is that many of the substitutions/etc. happen as targets are processed and the list of targets isn't necessarily known without actually attempting a build (at least to an extent) so it isn't necessarily possible to fully expand/etc. a makefile in-place.

The make -d output is also useful for certain incidental information related to how make has processed the makefiles but doesn't contain makefile contents directly.

Remake might also be able to provide some extra useful information.

If you are looking for the computed value of some assembled/etc. global make variable then this blog post by Eric Melski is likely to be very helpful.

tl;dr It adds a target like this to the Makefile (though there's more magic in the blog post so I suggest reading it).

print-%:
    @echo '$*=$($*)'
    @echo '  origin = $(origin $*)'
    @echo '  flavor = $(flavor $*)'
    @echo '   value = $(value  $*)'

Though in personal use I replaced that first line with something more like this

@echo '$*=$(subst ','\'',$($*))'

to keep the quoting of the result correct.

来源：https://stackoverflow.com/questions/31121698/gnu-makefile-preprocessor