问题
What is the reason Cortex-M3 has the initial stack pointer value located at 0x0, and reset handler located at 0x4? What is the design justification for this?
Why couldn't the ARM guys leave 0x0 to the reset handler like they do for Cortex-A, then initialize SP inside the reset handler?
回答1:
I think this one falls under the "it's not a bug, it's a feature" banner.
The ARM architecture M (microcontroller) profile has a completely different exception model to the A and the R profiles. The A-profile (like the R-profile) retain backwards compatibility with previous ARM processors. The M-profile was permitted to deviate from this, and so was designed to be easier to program completely from C/C++ (without asm).
Thus vector entries containing addresses rather than instructions, and once you've done that, why not set the SP in the same way? It also does automatic state saving on exception entry.
回答2:
everything unixsmurf said...
The traditional arm approach was a little strange, the typical approach is a list of addresses, not a table of instructions. So that may have been a factor. But they created a gobzillion interrupts not just the one (the vector table is 128/256 deep not just a handful) and no doubt you dont want to have to wrap every interrupt before calling C so the vector table, the changes in/lack of modes, and preserving registers for you, puts this package all together. You can put the address of the C handler right in the table, including the reset vector, to get the reset vector in there you need to have at a bare minimum set the stack pointer before calling, thus you need a spot for the user to indicate the initial value for the stack pointer.
来源：https://stackoverflow.com/questions/27189442/why-is-the-reset-handler-located-at-0x0-for-cortex-a-but-not-for-cortex-m3