Does VHDL have a ternary operator?

问题

I love the neatness of the ternary operator vs if clauses.

Does this operator exist in vhdl? My search was to the contrary. I also checked the when statement out, but it's not an operator, and I want to be able to use it in processes, too...

回答1:

No. It was discussed for VHDL-2008, but didn't get in. You've got a couple of options. If your tools support VHDL-2008, conditional assignments are now supported as sequential statements (they were previously just concurrent), so you can write something like:

process(clock)
begin
  if rising_edge(clock) then
    q <= '0' when reset else d; -- ie. much like q <= reset? '0':d;
  end if;
end process;

If you haven't got 2008, just write a function (q <= sel(reset, '0', d)). You have to write it for every type you're interested in, though.

回答2:

Not the one like you know from C/C++ but you can use:

destination <= signal1 when condition else signal2;

回答3:

In my utility package, I have these 2 function. For me, they're very handy

  function ternu(cond : boolean; res_true, res_false : unsigned) return unsigned is
  begin
     if cond then return res_true;
     else      return res_false;
     end if;
  end function;

  function terni(cond : boolean; res_true, res_false : integer) return integer is
  begin
     if cond then return res_true;
     else      return res_false;
     end if;
  end function;

来源：https://stackoverflow.com/questions/16112469/does-vhdl-have-a-ternary-operator