virtual-memory

Currently, I am trying to understand the value of splice/vmsplice. Regarding the use case of IPC, I stumbled upon the following answer on stackoverflow: https://stackoverflow.com/a/1350550/1305501 Question: How to transfer memory pages from one process to another process using vmsplice without copying data (i.e. zero-copy)? The answer mentioned above claims that it is possible. However, it doesn't contain any source code. If I understand the documentation of vmsplice correctly, the following function will transfer the memory pages into a pipe (kernel buffer) without copying, if the memory is

Given : 64 bit virtual byte address, 16 KB pages, 32-bit physical byte address. What is the total size of page table on this machine, assuming that the valid, protection, dirty and use bits take a total of 4 bits and all virtual pages are in use. So far I know the total number of page table entries : 2^64 / 2^14 = 2^50, but am not able to understand how to find the size of each entry. Each entry does contain 4 bits as said in the question, but can the size rest of the entry be found from the physical byte address? I'm confused in this part. Thanks. See below one method of calculating page

Prologue I am an operating system hobbyist, and my kernel runs on 80486+, and already supports virtual memory. Starting from 80386, the x86 processor family by Intel and various clones thereof has supported virtual memory with paging. It is well known that when the PG bit in CR0 is set, the processor uses virtual address translation. Then, the CR3 register points to the top-level page directory, that is the root for 2-4 levels of page table structures that map the virtual addresses to physical addresses. The processor does not consult these tables for each virtual address generated, instead

Once again, I find myself with a set of broken assumptions . The article itself is about a 10x performance gain by modifying a proven-optimal algorithm to account for virtual memory: On a modern multi-issue CPU, running at some gigahertz clock frequency, the worst-case loss is almost 10 million instructions per VM page fault. If you are running with a rotating disk, the number is more like 100 million instructions. What good is an O(log2(n)) algorithm if those operations cause page faults and slow disk operations? For most relevant datasets an O(n) or even an O(n^2) algorithm, which avoids

I'm trying to understand how does an operating system work when we want to assign some value to a particular virtual memory address. My first question concerns whether the MMU handles everything between the CPU and the RAM. Is this true? From what one can read from Wikipedia, I'd say so: A memory management unit (MMU), sometimes called paged memory management unit (PMMU), is a computer hardware component responsible for handling accesses to memory requested by the CPU. If that is the case, how can one tell the MMU I want to get 8 bytes, 64 or 128bytes, for example? What about writing? If that

Consider a virtual memory system with a 38-bit virtual byte address, 1KB pages and 512 MB of physical memory. What is the total size of the page table for each process on this machine, assuming that the valid, protection, dirty and use bits take a total of 4 bits, and that all the virtual pages are in use? (assume that disk addresses are not stored in the page table.) Well, if the question is simply "what is the size of the page table?" irrespective of whether it will fit into physical memory, the answer can be calculated thus: First physical memory. There are 512K pages of physical memory

Relation between cache size and page size How does the associativity and page size constrain the Cache size in virtually addressed cache architecture? Particularly I am looking for an example on the following statement: If C≤(page_size x associativity), the cache index bits come only from page offset (same in Virtual address and Physical address). Peter Cordes Intel CPUs have used 8-way associative 32kiB L1D with 64B lines for many years, for exactly this reason. Pages are 4k, so the page offset is 12 bits, exactly the same number of bits that make up the index and offset within a cache line.

My compilation fails on ubuntu 12.10 with 300mb memory available (750mb total, 350mb to MySQL), 1.5ghz, I am trying to rework wt's basic hello world file into a simple ajax page. I'm pretty sure it's not a memory issue at heart since I was able to compile the original hello.C file with g++ -O3 -o hello hello.C -lwtfcgi -lwt -lboost_signals . I'm sure I'm screwing up the c++ since I ripped out the guts of HelloApplication::HelloApplication(const WEnvironment& env) : WApplication(env) and put in the example from the Wt::Json example HelloApplication::HelloApplication(const WEnvironment& env) :

I need to allocate large regions of memory (megabytes) with large alignments (also potentially in the megabyte range). The VirtualAlloc family of functions don't seem to provide options to do this. What I do on Linux to achieve this is to mmap a larger region - large enough to guarantee that a sufficiently large region with the required alignment will be contained in it - and then munmap the regions at the beginning and the end of the large region that are not needed. As an example, let's say I need 4 megabytes, aligned on a 1 megabyte boundary (i.e. the start of the region having zeroes in