Possible to simulate a simple CPU in prolog?
问题 My understanding is that a simple model of a CPU is a state machine. When I look at prolog, it appears to tree-search (or graph search) combinations, whilst stopping at constraints running until its goals are found. I've been told that you can simulate a simple CPU in prolog. Is it possible to represent a state machine model like a simple CPU in prolog? 回答1: Prolog is a Turing-complete language, so you can express arbitrary computations in it, including the simulation of a CPU. You can