string-substitution

I've the following Makefile where I'd like to use Bash parameter substitution syntax as below: SHELL:=/bin/bash Foo=Bar all: @echo ${Foo} @echo ${Foo/Bar/OK} However it doesn't work as expected, as the output of the second echo command is empty: $ make Bar (empty) Although it works fine when invoking in shell directly: $ Foo=Bar; echo ${Foo/Bar/OK} OK How can I use the above syntax in Makefile? If you want the shell to expand the variable you have to use a shell variable, not a make variable. ${Foo/Bar/OK} is a make variable named literally Foo/Bar/OK . If you want to use shell variable

Have a file eg. Inventory.conf with lines like: Int/domain—home.dir=/etc/int I need to replace / and — before the = but not after. Result should be: Int_domain_home_dir=/etc/int I have tried several sed commands but none seem to fit my need. SLePort Sed with a t loop (BRE): $ sed ':a;s/[-/—.]\(.*=\)/_\1/;ta;' <<< "Int/domain—home.dir=/etc/int" Int_domain_home_dir=/etc/int When one of the -/—. character is found, it's replaced with a _ . Following text up to = is captured and output using backreference. If the previous substitution succeeds, the t command loops to label :a to check for further