sse2

elma and elmc are both unsigned long arrays. So are res1 and res2 . unsigned long simdstore[2]; __m128i *p, simda, simdb, simdc; p = (__m128i *) simdstore; for (i = 0; i < _polylen; i++) { u1 = (elma[i] >> l) & 15; u2 = (elmc[i] >> l) & 15; for (k = 0; k < 20; k++) { //res1[i + k] ^= _mulpre1[u1][k]; //res2[i + k] ^= _mulpre2[u2][k]; simda = _mm_set_epi64x (_mulpre2[u2][k], _mulpre1[u1][k]); simdb = _mm_set_epi64x (res2[i + k], res1[i + k]); simdc = _mm_xor_si128 (simda, simdb); _mm_store_si128 (p, simdc); res1[i + k] = simdstore[0]; res2[i + k] = simdstore[1]; } } Within the for loop is

I deal with image processing. I need to divide 16-bit integer SSE vector by 255. I can't use shift operator like _mm_srli_epi16(), because 255 is not a multiple of power of 2. I know of course that it is possible convert integer to float, perform division and then back conversion to integer. But might somebody knows another solution... There is an integer approximation of division by 255: inline int DivideBy255(int value) { return (value + 1 + (value >> 8)) >> 8; } So with using of SSE2 it will look like: inline __m128i DivideI16By255(__m128i value) { return _mm_srli_epi16(_mm_add_epi16( _mm

I just started to use SS2 optimization of image processing, but for the 3 channel 24 bit color images have no idea. My pix data arranged by BGR BGR BGR ... ,unsigned char 8-bi, so if I want to implement the Color2Gray with SSE2/SSE3/SSE4's instruction C/C++ fun ,how would I do? Does need to align(4/8/16) for my pix data? I have read article: http://supercomputingblog.com/windows/image-processing-with-sse/ But it is ARGB 4 channel 32-bit color,exactly process 4 color pix data every time. Thanks! //Assume the original pixel: unsigned char* pDataColor=(unsigned char*)malloc(src.width*src.height*3

I've added x64 configuration to my C++ project to compile 64-bit version of my app. Everything looks fine, but compiler gives the following warning: `cl : Command line warning D9002 : ignoring unknown option '/arch:SSE2'` Is there SSE2 optimization really not available for 64-bit projects? Seems to be all 64-bit processors has SSE2. Since compiler option always switched on by default no need to switch it on manually. From Wikipedia : SSE instructions : The original AMD64 architecture adopted Intel's SSE and SSE2 as core instructions. SSE3 instructions were added in April 2005. SSE2 replaces

I am somehow confused by the MOVSD assembly instruction. I wrote some numerical code computing some matrix multiplication, simply using ordinary C code with no SSE intrinsics. I do not even include the header file for SSE2 intrinsics for compilation. But when I check the assembler output, I see that: 1) 128-bit vector registers XMM are used; 2) SSE2 instruction MOVSD is invoked. I understand that MOVSD essentially operates on single double precision floating point. It only uses the lower 64-bit of an XMM register and set the upper 64-bit 0. But I just don't understand two things: 1) I never