simd

Suppose we have an std::vector , or any other sequence container (sometimes it will be a deque), which store uint64_t elements. Now, let's see this vector as a sequence of size() * 64 contiguous bits. I need to find the word formed by the bits in a given [begin, end) range, given that end - begin <= 64 so it fits in a word. The solution I have right now finds the two words whose parts will form the result, and separately masks and combines them. Since I need this to be as efficient as possible, I've tried to code everything without any if branch to not cause branch mispredictions, so for

I try to vectorize a CBRNG which uses 64bit widening multiplication. static __inline__ uint64_t mulhilo64(uint64_t a, uint64_t b, uint64_t* hip) { __uint128_t product = ((__uint128_t)a)*((__uint128_t)b); *hip = product>>64; return (uint64_t)product; } Is such a multiplication exists in a vectorized form in AVX2? No. There's no 64 x 64 -> 128 bit arithmetic as a vector instruction. Nor is there a vector mulhi type instruction (high word result of multiply). [V]PMULUDQ can do 32 x 32 -> 64 bit by only considering every second 32 bit unsigned element, or unsigned doubleword, as a source, and

I am trying to program the matrix multiplication in C using simd intrinsics. I was pretty sure of my implementation, but when I execute, i get some numerical errors starting from the 5th digit of the resulting matrix's coefficients. REAL_T is just a float with typedef /* This is my matmul Version with simd, using floating simple precision*/ void matmul(int n, REAL_T *A, REAL_T *B, REAL_T *C){ int i,j,k; __m256 vA, vB, vC, vRes; for (i=0; i<n; i++){ for (j=0; j<n; j++){ for (k=0; k<n; k= k+8){ vA = _mm256_load_ps(&A[i*n+k]); vB = _mm256_loadu_ps(&B[k*n+j]); vC = _mm256_mul_ps(vA, vB); vC =

I use Visual Studio with DiretX XNA math library. Now, I use GNU compiler collection. Advise me a SIMD math library with a good documentation. Eigen http://eigen.tuxfamily.org/index.php?title=Main_Page It supports SIMD extensions out of the box, it is well documented, it is quite flexible, it provides a lot of quality implementation of linear algebra methods, and have all the overloaded operators goodness. I've used it for several science-related projects, was very happy, especially after playing with others libraries. There is NT2 library. http://nt2.sourceforge.net/ This library has plan,

The code i want to optimize is basically a simple but large arithmetic formula, it should be fairly simple to analyze the code automatically to compute the independent multiplications/additions in parallel, but i read that autovectorization only works for loops. I've read multiple times now that access of single elements in a vector via union or some other way should be avoided at all costs, instead should be replaced by a _mm_shuffle_pd (i'm working on doubles only)... I don't seem to figure out how I can store the content of a __m128d vector as doubles without accessing it as a union. Also,

Assuming I have SSE to SSE4.1, but not AVX(2), what is the fastest way to load a packed memory layout like this (all 32-bit integers): a0 b0 c0 d0 a1 b1 c1 d1 a2 b2 c2 d2 a3 b3 c3 d3 Into four vectors a, b, c, d ? a: {a0, a1, a2, a3} b: {b0, b1, b2, b3} c: {c0, c1, c2, c3} d: {d0, d1, d2, d3} I'm not sure whether this is relevant or not, but in my actual application I have 16 vectors and as such a0 and a1 are 16*4 bytes apart in memory. What you need here is 4 loads followed by a 4x4 transpose: #include "emmintrin.h" // SSE2 v0 = _mm_load_si128((__m128i *)&a[0]); // v0 = a0 b0 c0 d0 v1 = _mm

I'm trying to vectorize some extremely performance critical code. At a high level, each loop iteration reads six floats from non-contiguous positions in a small array, then converts these values to double precision and adds them to six different double precision accumulators. These accumulators are the same across iterations, so they can live in registers. Due to the nature of the algorithm, it's not feasible to make the memory access pattern contiguous. The array is small enough to fit in L1 cache, though, so memory latency/bandwidth isn't a bottleneck. I'm willing to use assembly language or

Given a register of 4 bytes (or 16 for SIMD), there has to be an efficient way to sort the bytes in-register with a few instructions. Thanks in advance. Look up an efficient sorting network for N = the number of bytes you care about (4 or 16). Convert that to a sequence of compare and exchange instructions. (For N=16 that'll be more than 'a few', though.) Found it! It's in the 2007 paper "Using SIMD Registers and Instructions to Enable Instruction-Level Parallelism in Sorting Algorithms" by Furtak, Amaral, and Niewiadomski. Section 4. It uses 4 SSE registers, has 12 steps, and runs in 19