Access top level resources outside of hierarchy
问题 is there a way to synthesize an architecture in verilog such that a deeply nested endpoint can access some top level pins (from a .ucf) without expressly routing the pins through every module of the hierarchy. In my case i have a PCIe block with a deeply nested endpoint. AT the endpoint there have an address decoder that needs to provide some signal information from pins at the top level. I'd rather not modify every intervening module to carry the necessary wires. my web searches are