opcode

Invalid combination of opcode and operands [duplicate]

六眼飞鱼酱① 提交于 2019-12-02 10:48:11
问题 This question already has an answer here : Invalid combination of opcode and operands error (1 answer) Closed 3 years ago . SEGMENT .data print db "%d %d %d %d This is a test of printf", 10, 0 rowm dw 160 ;row multiplier iterations db 80 ;number of columns to set SEGMENT .bss offs resd 1 ;offset SEGMENT .text attribute equ 47h ;color attribute global _VText global _VPage extern _vm_buffer extern _printf _VText: push ebp mov ebp, esp push edi push esi push eax push es push ecx push edx mov esi

Invalid combination of opcode and operands [duplicate]

百般思念 提交于 2019-12-02 03:05:50
This question already has an answer here: Invalid combination of opcode and operands error 1 answer SEGMENT .data print db "%d %d %d %d This is a test of printf", 10, 0 rowm dw 160 ;row multiplier iterations db 80 ;number of columns to set SEGMENT .bss offs resd 1 ;offset SEGMENT .text attribute equ 47h ;color attribute global _VText global _VPage extern _vm_buffer extern _printf _VText: push ebp mov ebp, esp push edi push esi push eax push es push ecx push edx mov esi, [ebp+8] ;message mov es, [_vm_buffer] mov dword [offs], 0 mov ax, [ebp+12] ;row mul dword[rowm] ;multiply row by 160, result

What is the meaning of parentheses in opcodes in a NASM generated listing file?

无人久伴 提交于 2019-12-02 00:01:25
问题 When looking at a listing file that was generated by NASM, I see that there are three kinds of opcodes: Without parentheses. With round parentheses. With square parentheses. What they mean? when each of them is used? This is an example of a listing file that demonstrate all of the above: 1 section .text 2 extern printf 3 extern fgets 4 00000000 313233 str3: db "123" 5 main: 6 00000003 68[00000000] push str1 7 00000008 68[09000000] push str2 8 0000000D 68[00000000] push str3 9 00000012 E8

What is the meaning of parentheses in opcodes in a NASM generated listing file?

本秂侑毒 提交于 2019-12-01 21:45:12
When looking at a listing file that was generated by NASM, I see that there are three kinds of opcodes: Without parentheses. With round parentheses. With square parentheses. What they mean? when each of them is used? This is an example of a listing file that demonstrate all of the above: 1 section .text 2 extern printf 3 extern fgets 4 00000000 313233 str3: db "123" 5 main: 6 00000003 68[00000000] push str1 7 00000008 68[09000000] push str2 8 0000000D 68[00000000] push str3 9 00000012 E8(00000000) call func1 10 00000017 E8(04000000) call func2 11 0000001C E80B000000 call func3 12 00000021 E8

Checking up Intel assembly opcodes easily in Linux

↘锁芯ラ 提交于 2019-12-01 08:53:59
I have been looking for an practical tool that would print the opcodes of any Intel 64-bit or 32-bit instruction in Linux, eg. something like Hiew's assembler in DOS. A web-based service would be one option too. As I wasn't able to find any, I made my own bash script, that creates an assembly source file from command line parameters (instruction[s] and <32/64>), compiles, links and disassembles it and shows the correct rows of disassembly. But is there already some program that would show all the possible encodings for any given instruction, eg. for mov eax,ebx ? My approach using nasm , ld

Checking up Intel assembly opcodes easily in Linux

放肆的年华 提交于 2019-12-01 07:21:36
问题 I have been looking for an practical tool that would print the opcodes of any Intel 64-bit or 32-bit instruction in Linux, eg. something like Hiew's assembler in DOS. A web-based service would be one option too. As I wasn't able to find any, I made my own bash script, that creates an assembly source file from command line parameters (instruction[s] and <32/64>), compiles, links and disassembles it and shows the correct rows of disassembly. But is there already some program that would show all

decode ARM BL instruction

老子叫甜甜 提交于 2019-11-30 19:07:36
问题 I'm just getting started with the ARM architecture on my Nucleo STM32F303RE, and I'm trying to understand how the instructions are encoded. I have running a simple LED-blinking program, and the first few disassembled application instructions are: 08000188: push {lr} 0800018a: sub sp, #12 235 __initialize_hardware_early (); 0800018c: bl 0x80005b8 <__initialize_hardware_early> These instructions resolve to the following in the hex file (displayed weird in Eclipse -- each 32-bit word is in MSB

在RHEL/CentOS 6.3/5.6和Fedora 17/12上安装APC

岁酱吖の 提交于 2019-11-30 18:39:37
在RHEL/CentOS 6.3/5.6和Fedora 17/12上安装APC(可选的PHP缓存) APC (可选的PHP缓存)是一个免费,开源的PHP代码缓存。这个模块的主要目的是提供一个健壮的框架来缓存和优化PHP代码。 在Linux上安装和开启PHP APC 该说明文档描述了如何在 RHEL 6.3/6.2/6.1/6/5.8/5.6 , CentOS 6.3/6.2/6.1/6/5.8/5.6 和 Fedora 17,16,15,14,13,12上 使用 PECL 命令从代码仓库中下载,安装以及开启 APC 。 安装APC的依赖包 首先,我们需要安装所需的软件包,pecl,phpize和apxs命令,并使用YUM包管理工具来安装APC。 yum install php-pear php-devel httpd-devel pcre-devel gcc make 使用PECL安装APC 现在我们已经安装了所有必须的软件包以用来安装APC。接下来我们使用PECL命令来安装它。安装过程中请选择默认的设置值。 pecl install apc 输出如下: WARNING: channel "pecl.php.net" has updated its protocols, use "pecl channel-update pecl.php.net" to update

x86 32 bit opcodes that differ in x86-x64 or entirely removed

∥☆過路亽.° 提交于 2019-11-30 13:03:03
问题 I've looked up Wikipedia for x86 backward compatibility in x86-x64 and it says: x86-64 is fully backwards compatible with 16-bit and 32-bit x86 code.Because the full x86 16-bit and 32-bit instruction sets remain implemented in hardware without any intervening emulation, existing x86 executables run with no compatibility or performance penalties,whereas existing applications that are recoded to take advantage of new features of the processor design may achieve performance improvements. So I've

PHP Opcode Caching/Zend Acceleration and include_once vs. require_once

此生再无相见时 提交于 2019-11-30 10:08:15
I have a colleague who is looking into opcode caching/Zend Acceleration (I've always assumed these are the same thing) for our PHP based application. His Benchmarks appear to indicate that we're NOT seeing a performance benefit if we include our (large) class libraries with require_once, but we DO see the performance benefit when using include_once. This smells fishy to both of us, but I don't have time to check into our benchmark methodology myself and my colleague has more tolerance for the smell of fish than I do. :) Has anyone ever run into anything like this? If not, any thoughts on other