neon

I'm looking for the fastest way to test if a 128 NEON register contains all zeros, using NEON intrinsics. I'm currently using 3 OR operations, and 2 MOVs: uint32x4_t vr = vorrq_u32(vcmp0, vcmp1); uint64x2_t v0 = vreinterpretq_u64_u32(vr); uint64x1_t v0or = vorr_u64(vget_high_u64(v0), vget_low_u64(v0)); uint32x2_t v1 = vreinterpret_u32_u64 (v0or); uint32_t r = vget_lane_u32(v1, 0) | vget_lane_u32(v1, 1); if (r == 0) { // do stuff } This translates by gcc to the following assembly code: VORR q9, q9, q10 VORR d16, d18, d19 VMOV.32 r3, d16[0] VMOV.32 r2, d16[1] VORRS r2, r2, r3 BEQ ... Does anyone

I'm trying to understand the comment made by "Iwillnotexist Idonotexist" at SIMD optimization of cvtColor using ARM NEON intrinsics : ... why you don't use the ARM NEON intrisics that map to the VLD3 instruction? That spares you all of the shuffling, both simplifying and speeding up the code. The Intel SSE implementation requires shuffles because it lacks 2/3/4-way deinterleaving load instructions, but you shouldn't pass on them when they are available. The trouble I am having is the solution offers code that is non-interleaved, and it performs fused multiplies on floating points. I'm trying

How to use the NEON comparison instructions in general? Here is a case, I want to use, Greater-than-or-equal-to instruction? Currently I have a, int x; ... ... ... if(x >= 0) { .... } In NEON, I would like to use x in the same way, just that x this time is a vector. int32x4_t x; ... ... ... if(vcgeq_s32(x, vdupq_n_s32(0))) // Whats the best way to achieve this effect? { .... } With SIMD it's not straightforward to go from a single scalar if/then to a test on multiple elements. Usually you want to test if any element is greater than or if all elements are greater than, and there will usually be

my image processing project works with grayscale images. I have ARM Cortex-A8 processor platform. I want to make use of the NEON. I have a grayscale image( consider the example below) and in my alogorithm, I have to add only the columns. How can I load four 8-bit pixel values in parallel, which are uint8_t , as four uint32_t into one of the 128-bit NEON registers? What intrinsic do I have to use to do this? I mean: I must load them as 32 bits because if you look carefully, the moment I do 255 + 255 is 512, which can't be held in a 8-bit register. e.g. 255 255 255 255 ......... (640 pixels) 255

Here is a C++ code: #define ARR_SIZE_TEST ( 8 * 1024 * 1024 ) void cpp_tst_add( unsigned* x, unsigned* y ) { for ( register int i = 0; i < ARR_SIZE_TEST; ++i ) { x[ i ] = x[ i ] + y[ i ]; } } Here is a neon version: void neon_assm_tst_add( unsigned* x, unsigned* y ) { register unsigned i = ARR_SIZE_TEST >> 2; __asm__ __volatile__ ( ".loop1: \n\t" "vld1.32 {q0}, [%[x]] \n\t" "vld1.32 {q1}, [%[y]]! \n\t" "vadd.i32 q0 ,q0, q1 \n\t" "vst1.32 {q0}, [%[x]]! \n\t" "subs %[i], %[i], $1 \n\t" "bne .loop1 \n\t" : [x]"+r"(x), [y]"+r"(y), [i]"+r"(i) : : "memory" ); } Test function: void bench_simple_types

Checking gcc supports failed for neon instruction vadd.i16 q0,q0,q0 test.c int main () { __asm__("vadd.i16 q0, q0, q0"); return 0; } arm-linux-androideabi-gcc test.c /tmp/ccfc8m0G.s: Assembler messages: /tmp/ccfc8m0G.s:24: Error: bad instruction `vadd.i16 q0,q0,q0' Tried with flags -mcpu=cortex-a8 -mfpu=neon but stil no success Above code was used to test gcc support for neon instruction. Actually i am trying to build x264 with NEON support for ARM platformAfter running configure script x264 config log file contains Command line options: "--cross-prefix=arm-linux-androideabi-" "--enable-pic" "