microprocessors

A real question that I've been asking myself lately is what design choices brought about x86 being a little endian architecture instead of a big endian architecture? Largely, for the same reason you start at the least significant digit (the right end) when you add—because carries propagate toward the more significant digits. Putting the least significant byte first allows the processor to get started on the add after having read only the first byte of an offset. After you've done enough assembly coding and debugging you may come to the conclusion that it's not little endian that's the strange

In Linux world, to get nano seconds precision timer/clockticks one can use : #include <sys/time.h> int foo() { timespec ts; clock_gettime(CLOCK_REALTIME, &ts); //--snip-- } This answer suggests an asm approach to directly query for the cpu clock with the RDTSC instruction. In a multi-core, multi-processor architecture, how is this clock ticks/timer value synchronized across multiple cores/processors? My understanding is that there in inherent fencing being done. Is this understanding correct? Can you suggest some documentation that would explain this in detail? I am interested in Intel Nehalem

I want to know the difference between FIQ and IRQ interrupt system in any microprocessor, e.g: ARM926EJ. A feature of modern ARM CPUs (and some others). From the patent: A method of performing a fast interrupt in a digital data processor having the capability of handling more than one interrupt is provided. When a fast interrupt request is received a flag is set and the program counter and condition code registers are stored on a stack. At the end of the interrupt servicing routine the return from interrupt instructions retrieves the condition code register which contains the status of the