Which Intel microarchitecture introduced the ADC reg,0 single-uop special case?
ADC on Haswell and earlier is normally 2 uops, with 2 cycle latency, because Intel uops traditionally could only have 2 inputs ( https://agner.org/optimize/ ). Broadwell / Skylake and later have single-uop ADC/SBB/CMOV, after Haswell introduced 3-input uops for FMA and micro-fusion of indexed addressing modes in some cases. (But not for the adc al, imm8 short-form encoding, or the other al/ax/eax/rax, imm8/16/32/32 short forms with no ModRM. More details in my answer.) But adc with immediate 0 is special-cased on Haswell to decode as only a single uop. @BeeOnRope tested this , and included a