Pseudo Random Number Generator using LFSR in VHDL
问题 I'm having a bit of trouble creating a prng using the lfsr method. Here is my code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity pseudorng is Port ( clock : in STD_LOGIC; reset : in STD_LOGIC; Q : out STD_LOGIC_VECTOR (7 downto 0); check: out STD_LOGIC); constant seed: STD_LOGIC_VECTOR(7 downto 0) := "00000001"; end pseudorng; architecture Behavioral of pseudorng is signal temp: STD_LOGIC; signal Qt: STD_LOGIC_VECTOR(7 downto 0); begin PROCESS(clock) BEGIN IF rising_edge(clock) THEN IF