intrinsics

Temporary/“non-addressable” fixed-size array?

由 徘徊边缘 提交于 2019-12-07 10:34:46
问题 The title is in lack of a better name, and I am not sure I managed to explain myself clearly enough. I am looking for a way to access a "data type" via an index, but not force the compiler to keep it in an array. The problem occurs in writing a low-level code based on SSE/AVX intrinsics. For ease of programming I would like to write code as the following, with fixed-length loops over "registers" (data type __m512 ): inline void load(__m512 *vector, const float *in) { for(int i=0; i<24; i++)

Efficiently compute max of an array of 8 elements in arm neon

由 喜你入骨 提交于 2019-12-07 09:10:03
问题 How do I find max element in array of 8 bytes, 8 shorts or 8 ints? I may need just the position of the max element, value of the max element, or both of them. For example: unsigned FindMax8(const uint32_t src[8]) // returns position of max element { unsigned ret = 0; for (unsigned i=0; i<8; ++i) { if (src[i] > src[ret]) ret = i; } return ret; } At -O2 clang unrolls the loop but it does not use neon, which should give decent perf boost (because it eliminates many data dependent branches?) For

Matrix accessing and multiplication optimization for cpu

由 十年热恋 提交于 2019-12-07 07:44:40
问题 Im making some intrinsic optimized matrix-wrapper in java(with help of JNI). Needing affirmation of this, can you give some hints about matrix optimizations? What Im going to implement is: Matrix can be represented as four set of buffers/arrays, one for horizontal accessing, one for vertical accessing, one for diagonal access and a command buffer to compute elements of matrix only when needed. Here is an illustration. Matrix signature: 0 1 2 3 4 5 6 7 8 9 1 3 3 5 2 9 First(hroizontal) set:

What does “vperm v0,v0,v0,v17” with unused v0 do?

由 心已入冬 提交于 2019-12-07 05:30:15
问题 I'm working on an SHA-256 implementation using Power8 built-ins. The performance is off a bit. I estimate it is off by about 2 cycles per byte (cpb). The C/C++ code to perform SHA on a block looks like so: // Schedule 64-byte message SHA256_SCHEDULE(W, data); uint32x4_p8 a = abcd, e = efgh; uint32x4_p8 b = VectorShiftLeft<4>(a); uint32x4_p8 f = VectorShiftLeft<4>(e); uint32x4_p8 c = VectorShiftLeft<4>(b); uint32x4_p8 g = VectorShiftLeft<4>(f); uint32x4_p8 d = VectorShiftLeft<4>(c); uint32x4

How to store the contents of a __m128d simd vector as doubles without accessing it as a union?

由 青春壹個敷衍的年華 提交于 2019-12-07 03:46:31
问题 The code i want to optimize is basically a simple but large arithmetic formula, it should be fairly simple to analyze the code automatically to compute the independent multiplications/additions in parallel, but i read that autovectorization only works for loops. I've read multiple times now that access of single elements in a vector via union or some other way should be avoided at all costs, instead should be replaced by a _mm_shuffle_pd (i'm working on doubles only)... I don't seem to figure

Why is there no floating point intrinsic for `PSHUFD` instruction?

由 久未见 提交于 2019-12-06 08:52:58
The task I'm facing is to shuffle one _m128 vector and store the result in the other one. The way I see it, there are two basic ways to shuffle a packed floating point _m128 vector: _mm_shuffle_ps , which uses SHUFPS instruction that is not necessarily the best option if you want the values from one vector only: it takes two values from the destination operand, which implies an extra move. _mm_shuffle_epi32 , which uses PSHUFD instruction that seems to do exactly what is expected here and can have better latency/throughput than SHUFPS . The latter intrinsic however works with integer vectors (

Segmentation fault (core dumped) when using avx on an array allocated with new[]

由 孤街浪徒 提交于 2019-12-06 04:39:30
When I run this code in visual studio 2015, the code works correctly.But the code generates the following error in codeblocks : Segmentation fault(core dumped). I also ran the code in ubuntu with same error. #include <iostream> #include <immintrin.h> struct INFO { unsigned int id = 0; __m256i temp[8]; }; int main() { std::cout<<"Start AVX..."<<std::endl; int _size = 100; INFO *info = new INFO[_size]; for (int i = 0; i<_size; i++) { for (int k = 0; k < 8; k++) { info[i].temp[k] = _mm256_setr_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26,

Determine CPUID as listed in the Intel Intrinsics Guide

由 隐身守侯 提交于 2019-12-06 03:47:35
问题 In the Intel Intrinsics Guide there are 'Latency and Throughput Information' at the bottom of several Intrinsics, listing the performance for several CPUID(s). For example, the table in the Intrinsics Guide looks as follows for the Intrinsic _mm_hadd_pd : CPUID(s) Parameters Latency Throughput 0F_03 13 4 06_2A xmm1, xmm2 5 2 06_25/2C/1A/1E/1F/2E xmm1, xmm2 5 2 06_17/1D xmm1, xmm2 6 1 06_0F xmm1, xmm2 5 2 Now: How do I determine, what ID my CPU has? I'm using Kubuntu 12.04 and tried with sudo

Add saturate 32-bit signed ints intrinsics?

由 隐身守侯 提交于 2019-12-06 03:05:45
Can someone recommend a fast way to add saturate 32-bit signed integers using Intel intrinsics (AVX, SSE4 ...) ? I looked at the intrinsics guide and found _mm256_adds_epi16 but this seems to only add 16-bit ints. I don't see anything similar for 32 bits. The other calls seem to wrap around. A signed overflow will happen if (and only if): the signs of both inputs are the same, and the sign of the sum (when added with wrap-around) is different from the input Using C-Operators: overflow = ~(a^b) & (a^(a+b)) . Also, if an overflow happens, the saturated result will have the same sign as either

Best assembly or compilation for minimum of three values

由 风流意气都作罢 提交于 2019-12-06 01:54:11
问题 I'm looking at code generated by GCC-4.8 for x86_64 and wondering if there is a better (faster) way to compute the minimum of three values. Here's an excerpt from Python's collections module that computes the minimum of m , rightindex+1 , and leftindex : ssize_t m = n; if (m > rightindex + 1) m = rightindex + 1; if (m > leftindex) m = leftindex; GCC generates serially dependent code with CMOVs: leaq 1(%rbp), %rdx cmpq %rsi, %rdx cmovg %rsi, %rdx cmpq %rbx, %rdx cmovg %rbx, %rdx Is there
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