inline-assembly

Assembly: Unable to read sectors after the first track

有些话、适合烂在心里 提交于 2020-07-03 05:27:09
问题 As part of my operating system I wrote this read sector function. It takes a sector address to read from a BIOS device id. But when I set to read from sector 19 (Head: 0, Track: 1, Sector 2) the result at 0x1000:0x0000 is likely past that sector (I checked that several times with a hex viewer). Also, when I read more than one sector, so that sector 19 is included, at the address mentioned above, I can read sector 19 which is copied at 0x1000:(512*19) without a problem. void __NOINLINE

error: unsupported size for integer register

谁都会走 提交于 2020-06-29 03:39:16
问题 I'm using i686 gcc on windows. When I built the code with separate asm statements, it worked. However, when I try to combine it into one statement, it doesn't build and gives me a error: unsupported size for integer register . Here's my code u8 lstatus; u8 lsectors_read; u8 data_buffer; void operate(u8 opcode, u8 sector_size, u8 track, u8 sector, u8 head, u8 drive, u8* buffer, u8* status, u8* sectors_read) { asm volatile("mov %3, %%ah;\n" "mov %4, %%al;\n" "mov %5, %%ch;\n" "mov %6, %%cl;\n"

An implementation of std::atomic_thread_fence(std::memory_order_seq_cst) on x86 without extra performance penalties

二次信任 提交于 2020-06-16 19:09:40
问题 A following-up question for Why does this `std::atomic_thread_fence` work As a dummy interlocked operation is better than _mm_mfence , and there are quite many ways to implement it, which interlocked operation and on what data should be used? Assume using an inline assembly that is not aware of surrounding context, but can tell the compiler which registers it clobbers. 回答1: Short answer for now, without going into too much detail about why. See specifically the discussion in comments on that

An implementation of std::atomic_thread_fence(std::memory_order_seq_cst) on x86 without extra performance penalties

爷,独闯天下 提交于 2020-06-16 19:08:06
问题 A following-up question for Why does this `std::atomic_thread_fence` work As a dummy interlocked operation is better than _mm_mfence , and there are quite many ways to implement it, which interlocked operation and on what data should be used? Assume using an inline assembly that is not aware of surrounding context, but can tell the compiler which registers it clobbers. 回答1: Short answer for now, without going into too much detail about why. See specifically the discussion in comments on that

An implementation of std::atomic_thread_fence(std::memory_order_seq_cst) on x86 without extra performance penalties

强颜欢笑 提交于 2020-06-16 19:07:14
问题 A following-up question for Why does this `std::atomic_thread_fence` work As a dummy interlocked operation is better than _mm_mfence , and there are quite many ways to implement it, which interlocked operation and on what data should be used? Assume using an inline assembly that is not aware of surrounding context, but can tell the compiler which registers it clobbers. 回答1: Short answer for now, without going into too much detail about why. See specifically the discussion in comments on that

An implementation of std::atomic_thread_fence(std::memory_order_seq_cst) on x86 without extra performance penalties

隐身守侯 提交于 2020-06-16 19:07:04
问题 A following-up question for Why does this `std::atomic_thread_fence` work As a dummy interlocked operation is better than _mm_mfence , and there are quite many ways to implement it, which interlocked operation and on what data should be used? Assume using an inline assembly that is not aware of surrounding context, but can tell the compiler which registers it clobbers. 回答1: Short answer for now, without going into too much detail about why. See specifically the discussion in comments on that