How do I use the output of a program from an earlier part of a Stack/Cabal build as source in a later part of the same build?
问题 I have a very peculiar dependency situation that I would like to package up in a single Stack/Cabal package: I need to build and run my program to get the input to a code-generator which produces output that needs to be linked in to... my program. OK so in more concrete terms, here are the steps manually: stack build to install all dependencies, and build all non-Verilator-using executables. stack exec phase1 to run the first phase which generates, among other things, a Verilog file and a