digital-design

问题 I have the following source code from the CD attached with "Fundamental of Digital Design" book. When I tried run the program, it gave me the following error: Compiling Fig17_13.vhd... C:\Users\SPIDER\Desktop\EE460\The Final Project\Fig17_13.vhd(25): Warning C0007 : Architecture has unbound instances (ex. ct2) Done How can I fix this issue? Here is the code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity c74163test is port(ClrN

问题 I am attempting to program an addition and subtraction program in Verilog. Problem is Implementation and testing in Verilog of a module that performs Addition or Subtraction, then a Mux chooses between letting go through the result of one or the other, and then Decode the selected result from binary into a 7-segment Display format. Verilog Module will have 3 inputs: two 4-bit inputs named A and B, and a select input S. Your circuit should add the two numbers and should also subtract B from A

问题 lets say I have an n-bit array. I want to AND all elements in the array. Similar to wiring each element to an n-bit AND gate. How do I achieve this in VHDL? Note: I am trying to use re-usable VHDL code so I want to avoid hard coding something like result <= array(0) and array(1) and array(2)....and array(n); Thanks Oshara 回答1: Solution 1: With unary operator VHDL-2008 defines unary operators, like these: outp <= and "11011"; outp <= xor "11011"; outp <= and inp; --this would be your case