cortex-m

问题 I'm currently trying to understand ARM assembly for Cortex-M cores. I know that functions that are in Thumb mode (which is the only mode the core supports) are called by their address and the LSB of the address is high to indicate that the destination is Thumb code. In assembly I write following in front of the function "Reset_Handler" to tell the assembler that the data at the label is executable/a function: .type Reset_Handler, %function Reset_Handler: MOV R0, R0 # just do something If I

问题 I am trying to divide a 64 bits integral type to a 32 bits one, and I am using RVDS 4.1 as a tool-chain. Cortex-M0 does not have hardware divisor, so can I do the operation below? If so How? unsigned long int b = 2590202; unsigned long long int a = 953502716552001ULL; unsigned long long int result; result = a/b; 回答1: The compiler will compile the division operation as a call to a library subroutine that performs a software 64-bit division algorithm. You might have to also tell the compiler to

问题 I want to cross compile the gsl library for cortex m4 processor and use it in the lpc xpresso IDE for programming my board. I tried using the following command on linux terminal: ./configure --host=arm-none-eabi --build=x86_64-pc-linux-gnu --target=arm-none-eabi The output on terminal is: checking for a BSD-compatible install... /usr/bin/install -c checking whether build environment is sane... yes checking for arm-none-eabi-strip... arm-none-eabi-strip checking for a thread-safe mkdir -p...

问题 This question already has answers here : How do function pointers in C work? (11 answers) Closed 3 years ago . I am writing a bootloader for an ARM Cortex-M0 CPU. I need to forward the IRQs to the target app, unfortunately the IRQ vector in this CPU is at fixed address and I cannot relocate it, so I need a bit of trickery. I know the address where the addresses of the target app's IRQs are stored. So let's say, at address 0x5008 there's the address of void x_IRQHandler(void) (target app) What

问题 I tried below code, but failed to read the correct value from r11 following below reference of http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0472f/Cihfhjhg.html volatile int top_fp; __asm { mov top_fp, r11 } r11's value is 0x20009DCC top_fp's value is 0x00000004 [update] Solution, we have to use embedded assembler: __asm int getRegisterR11() { mov r0,r11 BX LR //return, must not omitted!!! } 回答1: The link you posted refers only to lr(R13), sp(R14), pc(R5) for legacy code

问题 I used "Exhuberant ctags" to index all the tags from my c-project. The c-project is embedded software for a Cortex-M7 microcontroller. The result is a tags-file. I'm trying to read this file and understand what is written down. Based on the documentation I find for ctags and Exhuberant ctags, I can grasp the meanings of most lines. For example: ADC3 .\Drivers\CMSIS\Device\ST\STM32F7xx\Include\stm32f767xx.h 1525;" d This line means: A tag has been found with name ADC3 . The tag is found in

问题 I'm working on bringing linux to a custom Cortex-M7 board with 16 Mb of SDRAM and 64 Mb of Flash. The platform has no-MMU, no shared libraries, FLAT executables. I'm having problems booting a Busybox system with very simple init.d shell scripts. The system is running out of memory by executing simple shell commands like "[" or "printf". It turns out that everytime one of these commands are executed the system needs to load the FULL, one and only busybox executable (650 Kb on my system). So

问题 I want to avoid nested interrupts at the interrupts entry in a CortexM based microcontroller. To achieve this I have an assembly file containing interrupt vectors and first instruction of each vector is the instruction ( CPSID I ) to disable interrupts globally. After every individual interrupt handler(written in C), execution returns to a common assembly routine which re-enables the interrupts with instruction CPSIE I and return from Interrupt/Exception process is triggered with instruction

问题 I'm trying to put a cortex m4 processor to sleep for a little less than a second. I want to be able to tell it to sleep, then a second later, or when a button is pressed, pick up right where I left off. I've looked in the reference manual and VLPS mode looks like it would fit my needs. I don't know how to begin to enter that mode or how to program the NVIC . More Info: I am doing this in C, on the bare metal. 回答1: You can download and inspect the code that implements this demo. Although the

问题 I'm programing a STM32F4 in C (gcc), it's a ARM Cortex M4, I see all examples finish their main() function with an infinite loop, even when the rest of the program will be executed from interruptions. If I try to remove the loop from my program, the interruptions stop being fired too. Why can't I just remove this loop and exit the main thread? here is the assembly (I guess it's thumb, but I can't read that, even with the doc): LoopFillZerobss: ldr r3, = _ebss cmp r2, r3 bcc FillZerobss /*