What do curly braces mean in Verilog?
问题 I am having a hard time understanding the following syntax in verilog: input [15:0] a; // 16-bit input output [31:0] result; // 32-bit output assign result = {{16{a[15]}}, {a[15:0]}}; I know the assign statement will wire something up to the result bus using wires and combinational logic, but what's up with the curly braces and 16{a[15]}? 回答1: The curly braces mean concatenation, from most significant bit (MSB) on the left down to the least significant bit (LSB) on the right. You are creating