computer-architecture

Assume a 5 stage pipeline architecture (IF = Instruction Fetch, ID = Instruction Decode, EX = Execute, MEM = Memory access, WB = Register write back).There are 4 instructions that has to be executed. (These sample instruction are not accurate, but I believe the point would be understood) In the fifth clock cycle, these instruction will be in pipeline as shown below. Add a, b, c [IF ID EX MEM WB] Add a, b, d [IF ID EX MEM] Add a, b, e [IF ID EX] Add a, b, f [IF ID] Now if an hardware interrupts occur what happens to these instructions. Will the interrupt be handled only after all the

From a previous question on this forum, I learned that in most of the memory systems, L1 cache is a subset of the L2 cache means any entry removed from L2 is also removed from L1. So now my question is how do I determine a corresponding entry in L1 cache for an entry in the L2 cache. The only information stored in the L2 entry is the tag information. Based on this tag information, if I re-create the addr it may span multiple lines in the L1 cache if the line-sizes of L1 and L2 cache are not same. Does the architecture really bother about flushing both the lines or it just maintains L1 and L2

I was trying to figure out how much memory I can malloc to maximum extent on my machine (1 Gb RAM 160 Gb HD Windows platform). I read that the maximum memory malloc can allocate is limited to physical memory (on heap). Also when a program exceeds consumption of memory to a certain level, the computer stops working because other applications do not get enough memory that they require. So to confirm, I wrote a small program in C: int main(){ int *p; while(1){ p=(int *)malloc(4); if(!p)break; } } I was hoping that there would be a time when memory allocation would fail and the loop would break,