avx

How can I disable auto-vectorization with AVX and FMA instructions? I would still prefer the compiler to employ SSE and SSE2 automatically, but not FMA and AVX. My code that uses AVX checks for its availability, but GCC doesn't do it when auto-vectorizing. So if I compile with -mfma and run the code on any CPU prior to Haswell I get SIGILL . How to solve this issue? What you want to do is compile different object files for each instruction set you are targeting. Then create a cpu dispatcher which asks CPUID for the available instruction set and then jumps to the appropriate version of the

I am trying to compile a program that uses the pclmulqdq instruction present in new Intel processors. I've installed GCC 4.6 using macports but when I compile my program (which uses the intrinsic _mm_clmulepi64_si128), I get /var/folders/ps/sfjmtgx5771_qbqnh4c9xclr0000gn/T//ccEAWWhd.s:16:no such instruction: `pclmulqdq $0, %xmm0,%xmm1' It seems that GCC is able to generate the correct assembly code from the instrinsic, but the assembler does not recognize the instruction. I've installed binutils using macports, but the problem persists. How do I know which assembler gcc is using? The XCode

I test the following simple function void mul(double *a, double *b) { for (int i = 0; i<N; i++) a[i] *= b[i]; } with very large arrays so that it is memory bandwidth bound. The test code I use is below. When I compile with -O2 it takes 1.7 seconds. When I compile with -O2 -mavx it takes only 1.0 seconds. The non vex-encoded scalar operations are 70% slower! Why is this? Here is the the assembly for -O2 and -O2 -mavx . https://godbolt.org/g/w4p60f System: i7-6700HQ@2.60GHz (Skylake) 32 GB mem, Ubuntu 16.10, GCC 6.3 Test code //gcc -O2 -fopenmp test.c //or //gcc -O2 -mavx -fopenmp test.c

Consider an array like atomic<int32_t> shared_array[] . What if you want to SIMD vectorize for(...) sum += shared_array[i].load(memory_order_relaxed) ?. Or to search an array for the first non-zero element, or zero a range of it? It's probably rare, but consider any use-case where tearing within an element is not allowed, but reordering between elements is fine. (Perhaps a search to find a candidate for a CAS). I think x86 aligned vector loads/stores would be safe in practice to use on for SIMD with mo_relaxed operations, because any tearing will only happen at 8B boundaries at worst on

Modern x86_64 linux with glibc will detect that CPU has support of AVX extension and will switch many string functions from generic implementation to AVX-optimized version (with help of ifunc dispatchers: 1 , 2 ). This feature can be good for performance, but it prevents several tool like valgrind ( older libVEXs , before valgrind-3.8 ) and gdb's " target record " ( Reverse Execution ) from working correctly (Ubuntu "Z" 17.04 beta, gdb 7.12 .50.20170207-0ubuntu2, gcc 6.3.0-8ubuntu1 20170221, Ubuntu GLIBC 2.24-7ubuntu2): $ cat a.c #include <string.h> #define N 1000 int main(){ char src[N], dst

Transposing a 8x8 matrix can be achieved by making four 4x4 matrices, and transposing each of them. This is not want I'm going for. In another question, one answer gave a solution that would only require 24 instructions for an 8x8 matrix. However, this does not apply to floats. Since the AVX2 contains registers of 256 bits, each register would fit eight 32 bits integers (floats). But the question is: How to transpose an 8x8 float matrix, using AVX/AVX2, with the smallest instructions possible? Z boson I already answered this question Fast memory transpose with SSE, AVX, and OpenMP . Let me