avx

Let's say I have a function written in c++ that performs matrix vector multiplications on a lot of vectors. It takes a pointer to the array of vectors to transform. Am I correct to assume that the compiler cannot efficiently optimize that to SIMD instructions because it does not know the alignment of the passed pointer (requiring a 16 byte alignment for SSE or 32 byte alignment for AVX) at compile time? Or is the memory alignment of the data irrelevant for optimal SIMD code and the data alignment will only affect cache performance? If alignment is important for the generated code, how can I

If I have 8 packed 32-bit floating point numbers ( __m256 ), what's the fastest way to extract the horizontal sum of all 8 elements? Similarly, how to obtain the horizontal maximum and minimum? In other words, what's the best implementation for the following C++ functions? float sum(__m256 x); ///< returns sum of all 8 elements float max(__m256 x); ///< returns the maximum of all 8 elements float min(__m256 x); ///< returns the minimum of all 8 elements Quickly jotted down here (and hence untested): float sum(__m256 x) { __m128 hi = _mm256_extractf128_ps(x, 1); __m128 lo = _mm256_extractf128

I'm writing some AVX code and I need to load from potentially unaligned memory. I'm currently loading 4 doubles , hence I would use intrinsic instruction _mm256_loadu_pd ; the code I've written is: __m256d d1 = _mm256_loadu_pd(vInOut + i*4); I've then compiled with options -O3 -mavx -g and subsequently used objdump to get the assembler code plus annotated code and line ( objdump -S -M intel -l avx.obj ). When I look into the underlying assembler code, I find the following: vmovupd xmm0,XMMWORD PTR [rsi+rax*1] vinsertf128 ymm0,ymm0,XMMWORD PTR [rsi+rax*1+0x10],0x1 I was expecting to see this:

Update: Please read the code, it is NOT about counting bits in one int Is it possible to improve performance of the following code with some clever assembler? uint bit_counter[64]; void Count(uint64 bits) { bit_counter[0] += (bits >> 0) & 1; bit_counter[1] += (bits >> 1) & 1; // .. bit_counter[63] += (bits >> 63) & 1; } Count is in the inner-most loop of my algorithm. Update: Architecture: x86-64, Sandy Bridge, so SSE4.2, AVX1 and older tech can be used, but not AVX2 or BMI1/2. bits variable has almost random bits (close to half zeros and half ones) Maybe you can do 8 at once, by taking 8 bits

I want to do a reduction on an array using OpenMP and SIMD. I read that a reduction in OpenMP is equivalent to: inline float sum_scalar_openmp2(const float a[], const size_t N) { float sum = 0.0f; #pragma omp parallel { float sum_private = 0.0f; #pragma omp parallel for nowait for(int i=0; i<N; i++) { sum_private += a[i]; } #pragma omp atomic sum += sum_private; } return sum; } I got this idea from the follow link: http://bisqwit.iki.fi/story/howto/openmp/#ReductionClause But atomic also does not support complex operators. What I did was replace atomic with critical and implemented the

I want to learn about parallel programming using Intel's Haswell CPU microarchitecture. About using SIMD: SSE4.2, AVX2 in asm/C/C++/(any other langs)?. Can you recommend books, tutorials, internet resources, courses? Thanks! Z boson It sounds to me like you need to learn about parallel programming in general on the CPU. I started looking into this about 10 months ago before I ever used SSE, OpenMP, or intrinsics so let me give a brief summary of some important concepts I have learned and some useful resources. There are several parallel computing technologies that can be employed: MIMD, SIMD,