avx

I've been using Intel's SSE intrinsics for quite some time with good performance gains. Hence, I expected the AVX intrinsics to further speed-up my programs. This, unfortunately, was not the case until now. Probably I am doing a stupid mistake, so I would be very grateful if somebody could help me out. I use Ubuntu 11.10 with g++ 4.6.1. I compiled my program (see below) with g++ simpleExample.cpp -O3 -march=native -o simpleExample The test system has a Intel i7-2600 CPU. Here is the code which exemplifies my problem. On my system, I get the output 98.715 ms, b[42] = 0.900038 // Naive 24.457 ms

Is there any good C/C++ tutorials or examples for learning Intel SSE and AVX instructions? I found few on Microsoft MSDN and Intel sites, but it would be great to understand it from the basics.. For the visually inclined SIMD programmer, Stefano Tommesani's site is the best introduction to x86 SIMD programming. http://www.tommesani.com/index.php/simd/46-sse-arithmetic.html The diagrams are only provided for MMX and SSE2, but once a learner gets proficient with SSE2, it is relatively easy to move on and read the formal specifications. Intel IA-32 Instructions beginning with A to M http://www

I am trying to profile my C++ code using perf tool. Implementation contains code with SSE/AVX/AVX2 instructions. In addition to that code is compiled with -O3 -mavx2 -march=native flags. I believe __memset_avx2_unaligned_erms function is a libc implementation of memset . perf shows that this function has considerable overhead. Function name indicates that memory is unaligned, however in the code I am explicitly aligning the memory using GCC built-in macro __attribute__((aligned (x))) What might be the reason for this function to have significant overhead and also why unaligned version is

As you know, the first two are AVX-specific intrinsics and the second is a SSE4.1 intrinsic. Both sets of intrinsics can be used to check for equality of 2 floating-point vectors. My specific use case is: _mm_cmpeq_ps or _mm_cmpeq_pd , followed by _mm_testc_ps or _mm_testc_pd on the result, with an appropriate mask But AVX provides equivalents for "legacy" intrinsics, so I might be able to use _mm_testc_si128 , after a cast of the result to __m128i . My questions are, which of the two use cases results in better performance and where I can find out what legacy SSE instructions are provided by

It is great that gcc compiler 4.8 comes with AVX optimization with -Ofast option. However, I found an interesting but stupid bug, that it adds additional computations which are unnecessary. Maybe I am wrong so can someone give me an explanation? The original C++ source code is as follows: #define N 1000007 float a[N],b[N],c[N],d[N],e[N]; int main(int argc, char *argv[]){ cout << a << ' ' << b << ' ' << c << endl; for(int x=0; x<N; ++x){ c[x] = 1/sqrt((a[x]+b[x]-c[x])*d[x]/e[x]); } return 0; } The code is compiled using g++ 4.8.4 in Ubuntu 14.04.3 x86_64: g++ -mavx avx.cpp -masm=intel -c -g -Wa

So, I want to set an individual bit of a __m256i register. Say, my __m256i contains: [ 1 0 1 0 | 1 0 1 0 | ... | 1 0 1 0 ] , how do I set and unset the n-th bit? ErmIg This is an implementation of function which can set individual bit inside a vector: #include <immintrin.h> #include <assert.h> void SetBit(__m256i & vector, size_t position, bool value) { assert(position <= 255); uint8_t lut[32] = { 0 }; lut[position >> 3] = 1 << (position & 7); __m256i mask = _mm256_loadu_si256((__m256i*)lut); if (value) vector = _mm256_or_si256(mask, vector); else vector = _mm256_andnot_si256(mask, vector); }

I had a C code written with some intel-intrinsincs. After I compiled it first with avx and then with ssse3 flags, I got two quite different assembly codes. E.g: AVX: vpunpckhbw %xmm0, %xmm1, %xmm2 SSSE3: movdqa %xmm0, %xmm2 punpckhbw %xmm1, %xmm2 It's clear that vpunpckhbw is just punpckhbw but using the avx three operand syntax. But is the latency and the throughput of the first instruction equivalent to the latency and the throughput of the last ones combined? Or does the answer depend on the architecture I'm using? It's IntelCore i5-6500 by the way. I tried to search for an answer in Agner

When I do a writemasked AVX-512 store, like so: vmovdqu8 [rsi] {k1}, zmm0 Will the instruction fault if some portion of the memory accessed at [rsi, rsi + 63] is not mapped but the writemask is zero for all those locations (i.e., the data is not actually modified due to the mask). Another way of asking it is if these AVX-512 masked stores have a similar fault suppression ability to vmaskmov introduced in AVX. No fault is raised if masked out elements touch invalid memory. Here's some Windows test code to prove that masking does indeed suppress memory faults. #include <immintrin.h> #include