avx512

I'm thinking of purchasing a Xeon Phi Knights Corner (KNC) coprocessor card . But I don't own an Intel Compiler and I have no interest in purchasing one (and the non-commercial version no longer seems to be an option). It appears that GCC is getting OpenMP support for the Xeon Phi . Is there some version of GCC or an extension to GCC that supports the KNC intrinsics ? Note that the 512-bit SIMD of the KNC is not compatible withe AVX512 (though the next version Knights Landing will be). You will have to use inline assembly rather than intrinsics to use the MIC vector instructions with GCC. The

I have a long chunk of memory, say, 256 KiB or longer. I want to count the number of 1 bits in this entire chunk, or in other words: Add up the "population count" values for all bytes. I know that AVX-512 has a VPOPCNTDQ instruction which counts the number of 1 bits in each consecutive 64 bits within a 512-bit vector, and IIANM it should be possible to issue one of these every cycle (if an appropriate SIMD vector register is available) - but I don't have any experience writing SIMD code (I'm more of a GPU guy). Also, I'm not 100% sure about compiler support for AVX-512 targets. On most CPUs,

So far I have managed to find out that: SSE and SSE2 are mandatory for Windows 8 and later (and of course for any 64-bit OS) AVX is only supported by Windows 7 SP1 or later Are there any caveats regarding using SSE3, SSSE3, SSE4.1, SSE 4.2, AVX2 and AVX-512 on Windows? Some clarification: I need this to determine what OSs will my program run on if I use instructions from one of the SSE/AVX sets. Peter Cordes Extensions that introduce new architectural state require special OS support, because the OS has to save/restore restore more data on context switches. So from the OSes perspective, there

Consider an array like atomic<int32_t> shared_array[] . What if you want to SIMD vectorize for(...) sum += shared_array[i].load(memory_order_relaxed) ?. Or to search an array for the first non-zero element, or zero a range of it? It's probably rare, but consider any use-case where tearing within an element is not allowed, but reordering between elements is fine. (Perhaps a search to find a candidate for a CAS). I think x86 aligned vector loads/stores would be safe in practice to use on for SIMD with mo_relaxed operations, because any tearing will only happen at 8B boundaries at worst on

Given a number in a register (a binary integer), how to convert it to a string of hexadecimal ASCII digits? Digits can be stored in memory or printed on the fly, but storing in memory and printing all at once is usually more efficient. (You can modify a loop that stores to instead print one at a time.) Can we efficiently handle all the nibbles in parallel with SIMD? (SSE2 or later?) 16 is a power of 2. Unlike decimal ( How do I print an integer in Assembly Level Programming without printf from the c library? ) or other bases that aren't a power of 2, we don't need division, and we can extract

While trying to answer Embedded broadcasts with intrinsics and assembly , I was trying to do something like this: __m512 mul_broad(__m512 a, float b) { int scratch = 0; asm( "vbroadcastss %k[scalar], %q[scalar]\n\t" // want vbr.. %xmm0, %zmm0 "vmulps %q[scalar], %[vec], %[vec]\n\t" // how it's done for integer registers "movw symbol(%q[inttmp]), %w[inttmp]\n\t" // movw symbol(%rax), %ax "movsbl %h[inttmp], %k[inttmp]\n\t" // movsx %ah, %eax : [vec] "+x" (a), [scalar] "+x" (b), [inttmp] "=r" (scratch) : : ); return a; } The GNU C x86 Operand Modifiers doc only specifies modifiers up to q (DI