avx2

I have been investigating the use of the new gather instructions of the AVX2 instruction set. Specifically, I decided to benchmark a simple problem, where one floating point array is permuted and added to another. In c, this can be implemented as void vectortest(double * a,double * b,unsigned int * ind,unsigned int N) { int i; for(i=0;i<N;++i) { a[i]+=b[ind[i]]; } } I compile this function with g++ -O3 -march=native. Now, I implement this in assembly in three ways. For simplicity I assume that the length of the arrays N is divisible by four. The simple, non-vectorized implementation: align 4

I want to learn about parallel programming using Intel's Haswell CPU microarchitecture. About using SIMD: SSE4.2, AVX2 in asm/C/C++/(any other langs)?. Can you recommend books, tutorials, internet resources, courses? Thanks! Z boson It sounds to me like you need to learn about parallel programming in general on the CPU. I started looking into this about 10 months ago before I ever used SSE, OpenMP, or intrinsics so let me give a brief summary of some important concepts I have learned and some useful resources. There are several parallel computing technologies that can be employed: MIMD, SIMD,

Is there a (fast) way to perform bits reverse of 32bit int values within avx2 register? E.g. _mm256_set1_epi32(2732370386); <do something here> //binary: 10100010110111001010100111010010 => 1001011100101010011101101000101 //register contains 1268071237 which is decimal representation of 1001011100101010011101101000101 Since I can't find a suitable dupe, I'll just post it. The main idea here is to make use of pshufb 's dual use a parallel 16-entry table lookup to reverse the bits of each nibble. Reversing bytes is obvious. Reversing the order of the two nibble in every byte could be done by

I want to shift SSE/AVX registers multiples of 32 bits left or right while shifting in zeros. Let me be more precise on the shifts I'm interested in. For SSE I want to do the following shifts of four 32bit floats: shift1_SSE: [1, 2, 3, 4] -> [0, 1, 2, 3] shift2_SSE: [1, 2, 3, 4] -> [0, 0, 1, 2] For AVX I want to shift do the following shifts: shift1_AVX: [1, 2, 3, 4, 5, 6, 7, 8] -> [0, 1, 2, 3, 4, 5, 6, 7] shift2_AVX: [1, 2, 3, 4, 5, 6, 7, 8] -> [0, 0, 1, 2, 3, 4, 5, 6] shift3_AVX: [1, 2, 3, 4 ,5 ,6, 7, 8] -> [0, 0, 0, 0, 1, 2, 3, 4] For SSE I have come up with the following code shift1_SSE =

vextracti128 and vextractf128 have the same functionality, parameters, and return values. In addition one is AVX instruction set while the other is AVX2. What is the difference? vextracti128 and vextractf128 have not only the same functionality, parameters, and return values. They have the same instruction length. And they have the same throughput (according to Agner Fog's optimization manuals). What is not completely clear is their latency values (performance in tight loops with dependency chains). Latency of instructions themselves is 3 cycles. But after reading section 2.1.3 ("Execution

The question: What is the most efficient sequence to generate a stride-3 gather of 32-bit elements from memory? If the memory is arranged as: MEM = R0 G0 B0 R1 G1 B1 R2 G2 B2 R3 G3 B3 ... We want to obtain three YMM registers where: YMM0 = R0 R1 R2 R3 R4 R5 R6 R7 YMM1 = G0 G1 G2 G3 G4 G5 G6 G7 YMM2 = B0 B1 B2 B3 B4 B5 B6 B7 Motivation and discussion The scalar C code is something like template <typename T> T Process(const T* Input) { T Result = 0; for (int i=0; i < 4096; ++i) { T R = Input[3*i]; T G = Input[3*i+1]; T B = Input[3*i+2]; Result += some_parallelizable_algorithm<T>(R, G, B); }

Suppose I'm using AVX2's VGATHERDPS - this should load 8 single-precision floats using 8 DWORD indices. What happens when the data to be loaded exists in different cache-lines? Is the instruction implemented as a hardware loop which fetches cache-lines one by one? Or, can it issue a load to multiple cache-lines at once? I read a couple of papers which state the former (and that's the one which makes more sense to me), but I would like to know a bit more about this. Link to one paper: http://arxiv.org/pdf/1401.7494.pdf I did some benchmarking of the AVX gather instructions and it seems to be a

I have a long chunk of memory, say, 256 KiB or longer. I want to count the number of 1 bits in this entire chunk, or in other words: Add up the "population count" values for all bytes. I know that AVX-512 has a VPOPCNTDQ instruction which counts the number of 1 bits in each consecutive 64 bits within a 512-bit vector, and IIANM it should be possible to issue one of these every cycle (if an appropriate SIMD vector register is available) - but I don't have any experience writing SIMD code (I'm more of a GPU guy). Also, I'm not 100% sure about compiler support for AVX-512 targets. On most CPUs,

I want to convert 8 bit integer to an array of size 8 with each value containing the bit value of an integer. For example: I have int8_t x = 8; I want to convert this to int8_t array_x = {0,0,0,0,1,0,0,0}; This has to be done efficiently, since this calculation is part of signal processing block. Is there a efficient way to do this? I did check the blend the instruction. It didn't suit my requirement when having array elements of size 8-bit. development platform is AMD Ryzen. "Inverse movemask" for a single byte with 0x00:0x01 formatted results, with SIMD but without BMI2. __m128i v = _mm_set1