atomicity

Does the C++11 memory model allow hoisting relaxed atomic loads out of loops?

六眼飞鱼酱① 提交于 2019-12-01 15:30:06
Consider the following code: #include <atomic> extern std::atomic<int> i; void f(void) { while (!i.load(std::memory_order_relaxed)) ; } I'm looking for a citation from the C++11 standard that says that the compiler is not allowed to transform the loop into if (!i.load(std::memory_order_relaxed)) { while (1) ; } I've seen some discussion here but nothing conclusive. Edit : A previous version of this post called an extern function inside the loop. Edit 2 : For motivation: The book "Effective Java" says that the HotSpot VM performs the following transformation: while (!done) i++; to if (!done)

Does the C++11 memory model allow hoisting relaxed atomic loads out of loops?

北战南征 提交于 2019-12-01 14:19:54
问题 Consider the following code: #include <atomic> extern std::atomic<int> i; void f(void) { while (!i.load(std::memory_order_relaxed)) ; } I'm looking for a citation from the C++11 standard that says that the compiler is not allowed to transform the loop into if (!i.load(std::memory_order_relaxed)) { while (1) ; } I've seen some discussion here but nothing conclusive. Edit : A previous version of this post called an extern function inside the loop. Edit 2 : For motivation: The book "Effective

feature request: an atomicAdd() function included in gwan.h

旧时模样 提交于 2019-12-01 09:48:42
问题 In the G-WAN KV options, KV_INCR_KEY will use the 1st field as the primary key. That means there is a function which increments atomically already built in the G-WAN core to make this primary index work. It would be good to make this function opened to be used by servlets, i.e. included in gwan.h. By doing so, ANSI C newbies like me could benefit from it. 回答1: There was ample discussion about this on the old G-WAN forum, and people were invited to share their experiences with atomic

Modular increment with Java's Atomic classes

人盡茶涼 提交于 2019-12-01 08:09:06
问题 I was surprised that Java's AtomicInteger and AtomicLong classes don't have methods for modular increments (so that the value wraps around to zero after hitting a limit). I figure I've got to be missing something obvious. What's the best way to do this? For example, I want to share a simple int between threads, and I want each thread to be able to increment it, say, mod 10. I can create a class which uses synchronization/locks, but is there a better, easier way? 回答1: What's difficult about

Atomically creating a file if it doesn't exist in Python

我们两清 提交于 2019-12-01 05:49:07
I am looking for an atomic version of the following: import os def tryMakeFile(filename): try: with open(filename) as _: return False except FileNotFoundError: with open(filename, mode='a') as _: return True (Please don't comment on stylistic issues here - I know this code is bad in many ways, but it suffices to illustrate my question.) In other words, I'm looking for a way to check if a file exists, and create it if it doesn't, in Python, in such a way that I know which happened. But done in such a way that there isn't a race condition between multiple processes (in my given example code, two

atomicity in 32/64 bit

*爱你&永不变心* 提交于 2019-12-01 05:46:51
the question is about when does a 64bit load/store operations are considered to be atomic. if i have a 64bit processor, but i'm using 32bit OS. Will i have 64bit atomicity? if i'm using 64bit OS but running an 32bit application (using WoW64), will i have 64bit atomicity? The application must be running on a 64bit OS and in native 64bit mode to gain the advantages of x64, unsurprisingly. If you're running in 32bit mode, either on a 32bit OS (with a 32bit app), you will get 32bit atomicity. If you're running 64bit mode on a 64bit OS on a 64bit CPU, you will get 64bit atomicity. All of the

x86-64 usage of LFENCE

拈花ヽ惹草 提交于 2019-12-01 05:30:19
I'm trying to understand the right way to use fences when measuring time with RDTSC/RDTSCP. Several questions on SO related to this have already been answered elaborately. I have gone through a few of them. I have also gone through this really helpful article on the same topic: http://www.intel.com/content/dam/www/public/us/en/documents/white-papers/ia-32-ia-64-benchmark-code-execution-paper.pdf However, in another online blog, there's an example of using LFENCE instead of CPUID on x86. I was wondering how LFENCE prevents earlier stores from contaminating the RDTSC measurements. E.g. <Instr A>

atomicity in 32/64 bit

独自空忆成欢 提交于 2019-12-01 04:44:12
问题 the question is about when does a 64bit load/store operations are considered to be atomic. if i have a 64bit processor, but i'm using 32bit OS. Will i have 64bit atomicity? if i'm using 64bit OS but running an 32bit application (using WoW64), will i have 64bit atomicity? 回答1: The application must be running on a 64bit OS and in native 64bit mode to gain the advantages of x64, unsurprisingly. If you're running in 32bit mode, either on a 32bit OS (with a 32bit app), you will get 32bit atomicity

Why is the << operation on an array in Ruby not atomic?

一曲冷凌霜 提交于 2019-12-01 03:13:32
In Ruby, this code is not threadsafe if array is modified by many threads: array = [] array << :foo # many threads can run this code Why is the << operation not thread safe? Grijesh Chauhan array is your program variable when you apply an operation like << to it. It happens in three-steps: The variable is first copied into a CPU register. The CPU performs computations. The CPU writes back the result to variable memory. So this high-level single-operation is performed in three steps. In between these steps, due to thread-context switching, other thread may read the same (old) value of the

ARM: Is writing/reading from int atomic?

耗尽温柔 提交于 2019-12-01 03:02:28
On ARM architecture, unfortunately I don't know exactly what chip it is, is a 32 bit int read/write atomic? Is there any sort of guarantees about reads/writes to basic types? It should be atomic, EXCEPT if that int is stored on a non-aligned address. old_timer This is documented either in the TRM for the core or in the AMBA/AXI spec. You need to look up the core being used from there if you can figure it out what flavor of AMBA/AXI bus and in that spec it spells out the atomic/non-atomic nature of each of the transaction types. For example the swp and ldrex/strex are atomic. An strd and stm