active-hdl

问题 From the Aldec Active-HDL GUI the vlib should create a work library, e.g.: vlib my_lib This creates a "my_lib" directory under the current directory, but with the warning: Warning: Cannot create library A subsequent set worklib my_lib fails with error "Error: Design not loaded.", and a compile with vcom -work my_lib tb.vhd completes without output and neither compiles anything to the "my_lib" directory. So it looks like even through a "my_lib" directory is created, it is not made available as

问题 Having a simple test bench like: entity tb is end entity; architecture syn of tb is signal show : boolean; begin show <= TRUE after 10 ns; end architecture; ModelSim GUI allows simulation and waveform viewing with a Tcl script in "all.do" with: vlib pit vcom -work pit tb.vhd vsim pit.tb add wave sim:/tb/show run 20 ns Where to do all.do in the ModelSim GUI console will make library, compile, load tb model, and show the waveform: How to make a similar simple Tcl script for a similar simulation

问题 This question already has an answer here : ACTIV HDL - VHDL-“Signal cannot be synthesized, bad synchronous description” (1 answer) Closed last year . I have a error while Synthesize this code in Xillinx. This error is: "Signal Z_1 cannot be synthesized, bad synchronous description" entity uk3 is port( rst : in BIT; C : in INTEGER; clk : in BIT; S : out INTEGER ); end uk3; --}} End of automatically maintained section architecture uk3 of uk3 is begin process (C,clk,rst) variable Z_1 : integer: